From a77cf69b9f71873dbe14fe4c53ae33d73371a769 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Fri, 3 May 2013 15:38:33 +0530 Subject: [PATCH] spi: zynq: Use divide by 8 baud rate for qspi dual stacked connection Currently the qspi dual stacked support is available on afx boards, there is a board hardware bug, that the controller will works on divide by 8. hence changed the master mode baud rate divisor to /8 incase of dual stacked mode qspi. Signed-off-by: Jagannadha Sutradharudu Teki --- drivers/spi/zynq_qspips.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/zynq_qspips.c b/drivers/spi/zynq_qspips.c index 057b289ed34..f185f97f079 100644 --- a/drivers/spi/zynq_qspips.c +++ b/drivers/spi/zynq_qspips.c @@ -265,6 +265,8 @@ static void xqspips_init_hw(int is_dual, unsigned int cs) config_reg = readl(&xqspips_base->confr); config_reg &= 0xFBFFFFFF; /* Set little endian mode of TX FIFO */ config_reg |= 0x8000FCC1; + if (is_dual == MODE_DUAL_STACKED) + config_reg |= 0x10; writel(config_reg, &xqspips_base->confr); if (is_dual == MODE_DUAL_PARALLEL) -- 2.47.3