From a8a5ea012471dd19ea9cb4d668c27ac678e84a3e Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 9 Jul 2025 12:08:58 +0200 Subject: [PATCH] arm64: dts: qcom: x1e80100: Add videocc Add the video clock controller for X1E80100, similar to sm8550.dtsi. It provides the needed clocks/power domains for the iris video codec. Reviewed-by: Bryan O'Donoghue Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-6-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4dba9f2b64f76..f293b13ecc0ce 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -5182,6 +5183,20 @@ }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,x1e80100-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; -- 2.47.3