From ab8264dc9c8b228a4c7071ba4974d06c43ece9f7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 Jul 2015 08:57:21 +0200 Subject: [PATCH] zynq: dts: Sync DTSes with the latest kernel and U-Boot Update dtses. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 68 ++--- arch/arm/dts/zynq-cc108.dts | 55 ++-- arch/arm/dts/zynq-zc702.dts | 409 +++++++++++++++++++++++++++++- arch/arm/dts/zynq-zc706.dts | 330 +++++++++++++++++++++++- arch/arm/dts/zynq-zc770-xm010.dts | 114 ++++++++- arch/arm/dts/zynq-zc770-xm011.dts | 72 +++--- arch/arm/dts/zynq-zc770-xm012.dts | 92 ++++++- arch/arm/dts/zynq-zc770-xm013.dts | 98 ++++++- arch/arm/dts/zynq-zed.dts | 83 +++++- arch/arm/dts/zynq-zybo.dts | 39 ++- 10 files changed, 1245 insertions(+), 115 deletions(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 3c3ae7a7094..853fa79a918 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -1,7 +1,10 @@ /* - * Copyright (C) 2011 - 2015 Xilinx, Inc. + * Xilinx Zynq 7000 DTSI + * Describes the hardware common to all Zynq 7000-based boards. * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2011 - 2015 Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ */ /include/ "skeleton.dtsi" @@ -132,16 +135,16 @@ L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; + interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; - mc0: memory-controller@f8006000 { + mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; - xlnx,has-ecc = <0x0>; }; ocmc: ocmc@f800c000 { @@ -177,6 +180,7 @@ interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; + spi-max-frequency = <166666700>; #address-cells = <1>; #size-cells = <0>; }; @@ -189,6 +193,7 @@ interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; + spi-max-frequency = <166666700>; #address-cells = <1>; #size-cells = <0>; }; @@ -233,27 +238,23 @@ }; gem0: ethernet@e000b000 { - compatible = "xlnx,ps7-ethernet-1.00.a"; + compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; - clocks = <&clkc 13>, <&clkc 30>; - clock-names = "ref_clk", "aper_clk"; - local-mac-address = [00 0a 35 00 00 00]; - xlnx,has-mdio = <0x1>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { - compatible = "xlnx,ps7-ethernet-1.00.a"; + compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; - clocks = <&clkc 14>, <&clkc 31>; - clock-names = "ref_clk", "aper_clk"; - local-mac-address = [00 0a 35 00 00 00]; - xlnx,has-mdio = <0x1>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; @@ -281,13 +282,12 @@ slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon"; + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - ps-clk-frequency = <33333333>; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", @@ -302,6 +302,12 @@ "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; + + pinctrl0: pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <&slcr>; + }; }; dmac_s: dmac@f8003000 { @@ -363,33 +369,33 @@ clocks = <&clkc 4>; }; - watchdog0: watchdog@f8005000 { - clocks = <&clkc 45>; - compatible = "xlnx,zynq-wdt-r1p2"; - device_type = "watchdog"; - interrupt-parent = <&intc>; - interrupts = <0 9 1>; - reg = <0xf8005000 0x1000>; - reset = <0>; - timeout-sec = <10>; - }; - usb0: usb@e0002000 { - clocks = <&clkc 28>; - compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; + clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; + phy_type = "ulpi"; }; usb1: usb@e0003000 { - clocks = <&clkc 29>; - compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; + clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; + phy_type = "ulpi"; + }; + + watchdog0: watchdog@f8005000 { + clocks = <&clkc 45>; + compatible = "cdns,wdt-r1p2"; + interrupt-parent = <&intc>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + timeout-sec = <10>; }; }; }; diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index eb5da525c61..038cb5773c2 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -26,13 +26,34 @@ chosen { bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = "/amba/serial@e0001000"; + linux,stdout-path = &uart1; + stdout-path = &uart1; }; memory@0 { device_type = "memory"; reg = <0x0 0x20000000>; }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@1 { + reg = <1>; + }; }; &qspi { @@ -74,36 +95,24 @@ }; }; -&usb0 { - status = "okay"; - dr_mode = "peripheral"; - phy_type = "ulpi"; - usb-reset = <&gpio0 9 0>; -}; - -&usb1 { +&sdhci1 { status = "okay"; - dr_mode = "host"; - phy_type = "ulpi"; + broken-cd ; + wp-inverted ; }; - -&gem0 { +&uart1 { status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - - phy0: phy@1 { - reg = <1>; - }; }; -&sdhci1 { +&usb0 { status = "okay"; - broken-cd ; - wp-inverted ; + dr_mode = "host"; + usb-phy = <&usb_phy0>; }; -&uart1 { +&usb1 { status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 4fa0b00b318..a7581602cfc 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -1,7 +1,8 @@ /* * Xilinx ZC702 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,417 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC702 Board"; + model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; }; memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; + + chosen { + bootargs = "earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw14 { + label = "sw14"; + gpios = <&gpio0 12 0>; + linux,code = <108>; /* down */ + gpio-key,wakeup; + autorepeat; + }; + sw13 { + label = "sw13"; + gpios = <&gpio0 14 0>; + linux,code = <103>; /* up */ + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds23 { + label = "ds23"; + gpios = <&gpio0 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&amba { + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + }; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + hwmon@52 { + compatible = "ti,ucd9248"; + reg = <52>; + }; + hwmon@53 { + compatible = "ti,ucd9248"; + reg = <53>; + }; + hwmon@54 { + compatible = "ti,ucd9248"; + reg = <54>; + }; + }; + }; +}; + +&pinctrl0 { + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_9_grp"; + }; + + conf { + groups = "can0_9_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO46"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO47"; + bias-disable; + }; + }; + + pinctrl_gem0_default: gem0-default { + mux { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + }; + + conf { + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + conf-rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + }; + + conf-mdio { + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: gpio0-default { + mux { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", + "gpio0_13_grp", "gpio0_14_grp"; + }; + + conf { + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", + "gpio0_13_grp", "gpio0_14_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-pull-up { + pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO7", "MIO8"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_10_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_10_grp"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_0_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + mux-wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "gpio0_15_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; + +&qspi { + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "n25q128a11"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 2a80195757d..5bcbc8cb1f7 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -1,7 +1,8 @@ /* * Xilinx ZC706 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,338 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC706 Board"; + model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; }; memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; + + chosen { + bootargs = "earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + ucd90120@65 { + compatible = "ti,ucd90120"; + reg = <0x65>; + }; + }; + }; +}; + +&pinctrl0 { + pinctrl_gem0_default: gem0-default { + mux { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + }; + + conf { + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + conf-rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + low-power-enable; + bias-disable; + }; + + mux-mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + }; + + conf-mdio { + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: gpio0-default { + mux { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; + }; + + conf { + groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-pull-up { + pins = "MIO46", "MIO47"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO7"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_10_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_10_grp"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_14_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_14_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + mux-wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "gpio0_15_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + num-cs = <1>; + flash@0 { + compatible = "n25q128a11"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 5e661749772..61c7fd7c5dd 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -1,7 +1,7 @@ /* * Xilinx ZC770 XM010 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2013 - 2015 Xilinx, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +9,121 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; + spi1 = &spi1; }; - memory { + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&qspi { + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "n25q128a11"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; }; }; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@0 { + compatible = "sst25wf080"; + reg = <1>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@test { + label = "spi-flash"; + reg = <0x0 0x100000>; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; + +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 0f1a5fc6452..cf54113f3f9 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -1,19 +1,12 @@ /* - * Device Tree Generator version: 1.1 + * Xilinx ZC770 XM013 board DTS * - * (C) Copyright 2007-2013 Xilinx, Inc. - * (C) Copyright 2007-2013 Michal Simek - * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd - * - * Michal SIMEK - * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 14.5 EDK_P.58f + * Copyright (C) 2013 Xilinx, Inc. * + * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; -/include/ "zynq-7000.dtsi" - +#include "zynq-7000.dtsi" / { compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; model = "Xilinx Zynq"; @@ -26,22 +19,33 @@ chosen { bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = "/amba/serial@e0001000"; + linux,stdout-path = &uart1; + stdout-path = &uart1; }; memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; }; -&smcc { +&can0 { status = "okay"; - arm,addr25 = <0x0>; - arm,nor-chip-sel0 = <0x0>; - arm,nor-chip-sel1 = <0x0>; - arm,sram-chip-sel0 = <0x0>; - arm,sram-chip-sel1 = <0x0>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; }; &nand0 { @@ -76,33 +80,27 @@ }; }; -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - -&usb1 { +&smcc { status = "okay"; - dr_mode = "host"; - phy_type = "ulpi"; + arm,addr25 = <0x0>; + arm,nor-chip-sel0 = <0x0>; + arm,nor-chip-sel1 = <0x0>; + arm,sram-chip-sel0 = <0x0>; + arm,sram-chip-sel1 = <0x0>; }; - -&can0 { +&spi0 { status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; }; -&i2c1 { +&uart1 { status = "okay"; - clock-frequency = <400000>; - - m24c02_eeprom@52 { - compatible = "at,24c02"; - reg = <0x52>; - }; }; -&uart1 { +&usb1 { status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 127a6619c63..82a0005ad2b 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -1,7 +1,7 @@ /* * Xilinx ZC770 XM012 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2013 - 2015 Xilinx, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +9,99 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; serial0 = &uart1; + spi0 = &spi1; }; - memory { + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; }; + +&can1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; +}; + +&nor0 { + status = "okay"; + bank-width = <1>; + xlnx,sram-cycle-t0 = <0xb>; + xlnx,sram-cycle-t1 = <0xb>; + xlnx,sram-cycle-t2 = <0x4>; + xlnx,sram-cycle-t3 = <0x4>; + xlnx,sram-cycle-t4 = <0x3>; + xlnx,sram-cycle-t5 = <0x3>; + xlnx,sram-cycle-t6 = <0x2>; + partition@nor-fsbl-uboot { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@nor-linux { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@nor-device-tree { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@nor-rootfs { + label = "nor-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@nor-bitstream { + label = "nor-bitstream"; + reg = <0xC00000 0x400000>; + }; +}; + +&smcc { + status = "okay"; + arm,addr25 = <0x1>; + arm,nor-chip-sel0 = <0x1>; + arm,nor-chip-sel1 = <0x0>; + arm,sram-chip-sel0 = <0x0>; + arm,sram-chip-sel1 = <0x0>; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index c61c7e7592f..a6e89be3921 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -9,15 +9,107 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; aliases { + ethernet0 = &gem1; + i2c0 = &i2c1; serial0 = &uart0; + spi0 = &qspi; + spi1 = &spi0; }; - memory { + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = &uart0; + stdout-path = &uart0; + }; + + memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; }; + +&can1 { + status = "okay"; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + si570: clock-generator@55 { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x55>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + num-cs = <1>; + flash@0 { + compatible = "n25q128a11"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + eeprom: at25@0 { + at25,byte-len = <8192>; + at25,addr-mode = <2>; + at25,page-size = <32>; + + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 70cc8a6c0d7..dae6d141707 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -1,7 +1,8 @@ /* * Xilinx ZED board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,91 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZED Board"; + model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; }; memory { device_type = "memory"; - reg = <0 0x20000000>; + reg = <0x0 0x20000000>; }; + + chosen { + bootargs = "earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&qspi { + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "n25q128a11"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 20e03867773..3be7086e3c3 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -1,7 +1,8 @@ /* * Digilent ZYBO board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,45 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZYBO Board"; - compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000"; + model = "Zynq ZYBO Development Board"; + compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; serial0 = &uart1; }; memory { device_type = "memory"; - reg = <0 0x20000000>; + reg = <0x0 0x20000000>; }; + + chosen { + bootargs = "earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + +}; + +&clkc { + ps-clk-frequency = <50000000>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; }; -- 2.47.3