From ad211501fff48d0cda35dd187aa7e356a4fb5581 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Thu, 10 Jul 2025 18:50:05 +0200 Subject: [PATCH] arm64: dts: exynos990: Enable watchdog timer Enable the two watchdog timer clusters (cl0, cl2) present on the Exynos990 SoC. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-1-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index dd7f99f51a754..4446a1a54ba2d 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -211,6 +211,30 @@ ; }; + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynos990-wdt"; + reg = <0x10050000 0x100>; + interrupts = ; + clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK>, + <&oscclk>; + clock-names = "watchdog", + "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + }; + + watchdog_cl2: watchdog@10060000 { + compatible = "samsung,exynos990-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK>, + <&oscclk>; + clock-names = "watchdog", + "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <2>; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; reg = <0x10101000 0x1000>, -- 2.47.3