From ae017975f87fcbdd874fe89be8dcc292830b8d3a Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Mon, 11 Dec 2023 13:11:19 -0500 Subject: [PATCH] Fixes for 6.1 Signed-off-by: Sasha Levin --- ...-drop-check-for-doublescan-mode-in-m.patch | 58 ++++ queue-6.1/drm-i915-lvds-use-reg_bit-co.patch | 130 ++++++++ ...op-caching-has_hdmi_monitor-in-struc.patch | 85 ++++++ ...me-timing-checks-on-bxt-glk-dsi-tran.patch | 284 ++++++++++++++++++ queue-6.1/series | 4 + 5 files changed, 561 insertions(+) create mode 100644 queue-6.1/drm-i915-display-drop-check-for-doublescan-mode-in-m.patch create mode 100644 queue-6.1/drm-i915-lvds-use-reg_bit-co.patch create mode 100644 queue-6.1/drm-i915-sdvo-stop-caching-has_hdmi_monitor-in-struc.patch create mode 100644 queue-6.1/drm-i915-skip-some-timing-checks-on-bxt-glk-dsi-tran.patch diff --git a/queue-6.1/drm-i915-display-drop-check-for-doublescan-mode-in-m.patch b/queue-6.1/drm-i915-display-drop-check-for-doublescan-mode-in-m.patch new file mode 100644 index 00000000000..bdb21195881 --- /dev/null +++ b/queue-6.1/drm-i915-display-drop-check-for-doublescan-mode-in-m.patch @@ -0,0 +1,58 @@ +From 802386a2ffea37e2e2ee2c680e02ef433c1f8029 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 17 Oct 2022 20:00:37 +0530 +Subject: drm/i915/display: Drop check for doublescan mode in modevalid + +From: Ankit Nautiyal + +[ Upstream commit 9d04eb20bc71a383b4d4e383b0b7fac8d38a2e34 ] + +Since the DP/HDMI connector do not set connector->doublescan_allowed, +the doublescan modes will get automatically filtered during +drm_helper_probe_single_connector_modes(). + +Therefore check for double scan modes is not required and is dropped +from modevalid functions for both DP and HDMI. + +Signed-off-by: Ankit Nautiyal +Reviewed-by: Jani Nikula +Signed-off-by: Uma Shankar +Link: https://patchwork.freedesktop.org/patch/msgid/20221017143038.1748319-2-ankit.k.nautiyal@intel.com +Stable-dep-of: 20c2dbff342a ("drm/i915: Skip some timing checks on BXT/GLK DSI transcoders") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_dp.c | 3 --- + drivers/gpu/drm/i915/display/intel_hdmi.c | 3 --- + 2 files changed, 6 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 594ea037050a9..fd7c360bb44d7 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -973,9 +973,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, + enum drm_mode_status status; + bool dsc = false, bigjoiner = false; + +- if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +- return MODE_NO_DBLESCAN; +- + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_H_ILLEGAL; + +diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c +index 7816b2a33feeb..4f31355d09a4e 100644 +--- a/drivers/gpu/drm/i915/display/intel_hdmi.c ++++ b/drivers/gpu/drm/i915/display/intel_hdmi.c +@@ -1987,9 +1987,6 @@ intel_hdmi_mode_valid(struct drm_connector *connector, + bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); + bool ycbcr_420_only; + +- if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +- return MODE_NO_DBLESCAN; +- + if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) + clock *= 2; + +-- +2.42.0 + diff --git a/queue-6.1/drm-i915-lvds-use-reg_bit-co.patch b/queue-6.1/drm-i915-lvds-use-reg_bit-co.patch new file mode 100644 index 00000000000..29af7a5ec01 --- /dev/null +++ b/queue-6.1/drm-i915-lvds-use-reg_bit-co.patch @@ -0,0 +1,130 @@ +From 3c3190fd67bf24c58cb78816b9dbf77c32465433 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Jan 2023 20:05:35 +0200 +Subject: drm/i915/lvds: Use REG_BIT() & co. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit 9dd56e979cb69f5cd904574c852b620777a2f69f ] + +Use REG_BIT() & co. for the LVDS port register. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20230130180540.8972-4-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +Stable-dep-of: 20c2dbff342a ("drm/i915: Skip some timing checks on BXT/GLK DSI transcoders") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_lvds.c | 4 +- + drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++------------ + 2 files changed, 24 insertions(+), 26 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c +index a749a5a66d624..e4606d9a25edb 100644 +--- a/drivers/gpu/drm/i915/display/intel_lvds.c ++++ b/drivers/gpu/drm/i915/display/intel_lvds.c +@@ -92,9 +92,9 @@ bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, + + /* asserts want to know the pipe even if the port is disabled */ + if (HAS_PCH_CPT(dev_priv)) +- *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; ++ *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); + else +- *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; ++ *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); + + return val & LVDS_PORT_EN; + } +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index 25015996f627a..c6766704340eb 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -2681,52 +2681,50 @@ + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as + * the DPLL semantics change when the LVDS is assigned to that pipe. + */ +-#define LVDS_PORT_EN (1 << 31) ++#define LVDS_PORT_EN REG_BIT(31) + /* Selects pipe B for LVDS data. Must be set on pre-965. */ +-#define LVDS_PIPE_SEL_SHIFT 30 +-#define LVDS_PIPE_SEL_MASK (1 << 30) +-#define LVDS_PIPE_SEL(pipe) ((pipe) << 30) +-#define LVDS_PIPE_SEL_SHIFT_CPT 29 +-#define LVDS_PIPE_SEL_MASK_CPT (3 << 29) +-#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) ++#define LVDS_PIPE_SEL_MASK REG_BIT(30) ++#define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe)) ++#define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) ++#define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe)) + /* LVDS dithering flag on 965/g4x platform */ +-#define LVDS_ENABLE_DITHER (1 << 25) ++#define LVDS_ENABLE_DITHER REG_BIT(25) + /* LVDS sync polarity flags. Set to invert (i.e. negative) */ +-#define LVDS_VSYNC_POLARITY (1 << 21) +-#define LVDS_HSYNC_POLARITY (1 << 20) ++#define LVDS_VSYNC_POLARITY REG_BIT(21) ++#define LVDS_HSYNC_POLARITY REG_BIT(20) + + /* Enable border for unscaled (or aspect-scaled) display */ +-#define LVDS_BORDER_ENABLE (1 << 15) ++#define LVDS_BORDER_ENABLE REG_BIT(15) + /* + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per + * pixel. + */ +-#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +-#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +-#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) ++#define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8) ++#define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0) ++#define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3) + /* + * Controls the A3 data pair, which contains the additional LSBs for 24 bit + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be + * on. + */ +-#define LVDS_A3_POWER_MASK (3 << 6) +-#define LVDS_A3_POWER_DOWN (0 << 6) +-#define LVDS_A3_POWER_UP (3 << 6) ++#define LVDS_A3_POWER_MASK REG_GENMASK(7, 6) ++#define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0) ++#define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3) + /* + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP + * is set. + */ +-#define LVDS_CLKB_POWER_MASK (3 << 4) +-#define LVDS_CLKB_POWER_DOWN (0 << 4) +-#define LVDS_CLKB_POWER_UP (3 << 4) ++#define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4) ++#define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0) ++#define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3) + /* + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 + * setting for whether we are in dual-channel mode. The B3 pair will + * additionally only be powered up when LVDS_A3_POWER_UP is set. + */ +-#define LVDS_B0B3_POWER_MASK (3 << 2) +-#define LVDS_B0B3_POWER_DOWN (0 << 2) +-#define LVDS_B0B3_POWER_UP (3 << 2) ++#define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2) ++#define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0) ++#define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3) + + /* Video Data Island Packet control */ + #define VIDEO_DIP_DATA _MMIO(0x61178) +@@ -6461,7 +6459,7 @@ + #define FDI_PLL_CTL_2 _MMIO(0xfe004) + + #define PCH_LVDS _MMIO(0xe1180) +-#define LVDS_DETECTED (1 << 1) ++#define LVDS_DETECTED REG_BIT(1) + + #define _PCH_DP_B 0xe4100 + #define PCH_DP_B _MMIO(_PCH_DP_B) +-- +2.42.0 + diff --git a/queue-6.1/drm-i915-sdvo-stop-caching-has_hdmi_monitor-in-struc.patch b/queue-6.1/drm-i915-sdvo-stop-caching-has_hdmi_monitor-in-struc.patch new file mode 100644 index 00000000000..b2f760468c6 --- /dev/null +++ b/queue-6.1/drm-i915-sdvo-stop-caching-has_hdmi_monitor-in-struc.patch @@ -0,0 +1,85 @@ +From 3b6a91726bd6493842b14b9ae38429f0e21c256a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 May 2023 12:08:19 +0300 +Subject: drm/i915/sdvo: stop caching has_hdmi_monitor in struct intel_sdvo + +From: Jani Nikula + +[ Upstream commit f2f9c8cb6421429ef166d6404426693212d0ca07 ] + +Use the information stored in display info. + +Reviewed-by: Ankit Nautiyal +Signed-off-by: Jani Nikula +Link: https://patchwork.freedesktop.org/patch/msgid/3e9e1dcd554d470bdf474891a431b15e1880f9a0.1685437500.git.jani.nikula@intel.com +Stable-dep-of: 20c2dbff342a ("drm/i915: Skip some timing checks on BXT/GLK DSI transcoders") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/intel_sdvo.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c +index 2c2e0f041f869..c1a85128911e1 100644 +--- a/drivers/gpu/drm/i915/display/intel_sdvo.c ++++ b/drivers/gpu/drm/i915/display/intel_sdvo.c +@@ -115,7 +115,6 @@ struct intel_sdvo { + + enum port port; + +- bool has_hdmi_monitor; + bool has_hdmi_audio; + + /* DDC bus used by this SDVO encoder */ +@@ -1278,10 +1277,13 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) + pipe_config->clock_set = true; + } + +-static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo, ++static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector, + const struct drm_connector_state *conn_state) + { +- return sdvo->has_hdmi_monitor && ++ struct drm_connector *connector = conn_state->connector; ++ ++ return intel_sdvo_connector->is_hdmi && ++ connector->display_info.is_hdmi && + READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; + } + +@@ -1360,7 +1362,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, + pipe_config->pixel_multiplier = + intel_sdvo_get_pixel_multiplier(adjusted_mode); + +- pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state); ++ pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state); + + if (pipe_config->has_hdmi_sink) { + if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO) +@@ -1875,7 +1877,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector, + struct intel_sdvo_connector *intel_sdvo_connector = + to_intel_sdvo_connector(connector); + int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; +- bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state); ++ bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); + int clock = mode->clock; + + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +@@ -2064,7 +2066,6 @@ intel_sdvo_tmds_sink_detect(struct drm_connector *connector) + if (edid->input & DRM_EDID_INPUT_DIGITAL) { + status = connector_status_connected; + if (intel_sdvo_connector->is_hdmi) { +- intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); + intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); + } + } else +@@ -2116,7 +2117,6 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) + + intel_sdvo->attached_output = response; + +- intel_sdvo->has_hdmi_monitor = false; + intel_sdvo->has_hdmi_audio = false; + + if ((intel_sdvo_connector->output_flag & response) == 0) +-- +2.42.0 + diff --git a/queue-6.1/drm-i915-skip-some-timing-checks-on-bxt-glk-dsi-tran.patch b/queue-6.1/drm-i915-skip-some-timing-checks-on-bxt-glk-dsi-tran.patch new file mode 100644 index 00000000000..f325875b0ad --- /dev/null +++ b/queue-6.1/drm-i915-skip-some-timing-checks-on-bxt-glk-dsi-tran.patch @@ -0,0 +1,284 @@ +From 94bf3d4d6899d24114d0a2d5afb8c1937cbb914a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Nov 2023 16:50:25 +0200 +Subject: drm/i915: Skip some timing checks on BXT/GLK DSI transcoders +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit 20c2dbff342aec13bf93c2f6c951da198916a455 ] + +Apparently some BXT/GLK systems have DSI panels whose timings +don't agree with the normal cpu transcoder hblank>=32 limitation. +This is perhaps fine as there are no specific hblank/etc. limits +listed for the BXT/GLK DSI transcoders. + +Move those checks out from the global intel_mode_valid() into +into connector specific .mode_valid() hooks, skipping BXT/GLK +DSI connectors. We'll leave the basic [hv]display/[hv]total +checks in intel_mode_valid() as those seem like sensible upper +limits regardless of the transcoder used. + +Cc: stable@vger.kernel.org +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9720 +Fixes: 8f4b1068e7fc ("drm/i915: Check some transcoder timing minimum limits") +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231127145028.4899-1-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +(cherry picked from commit e0ef2daa8ca8ce4dbc2fd0959e383b753a87fd7d) +Signed-off-by: Jani Nikula +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/icl_dsi.c | 7 +++++++ + drivers/gpu/drm/i915/display/intel_crt.c | 5 +++++ + drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++ + drivers/gpu/drm/i915/display/intel_display.h | 3 +++ + drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ + drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++++ + drivers/gpu/drm/i915/display/intel_dvo.c | 6 ++++++ + drivers/gpu/drm/i915/display/intel_hdmi.c | 4 ++++ + drivers/gpu/drm/i915/display/intel_lvds.c | 5 +++++ + drivers/gpu/drm/i915/display/intel_sdvo.c | 8 +++++++- + drivers/gpu/drm/i915/display/intel_tv.c | 8 +++++++- + drivers/gpu/drm/i915/display/vlv_dsi.c | 18 +++++++++++++++++- + 12 files changed, 79 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c +index 8219310025de5..f7422f0cf579d 100644 +--- a/drivers/gpu/drm/i915/display/icl_dsi.c ++++ b/drivers/gpu/drm/i915/display/icl_dsi.c +@@ -1500,6 +1500,13 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state, + static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) + { ++ struct drm_i915_private *i915 = to_i915(connector->dev); ++ enum drm_mode_status status; ++ ++ status = intel_cpu_transcoder_mode_valid(i915, mode); ++ if (status != MODE_OK) ++ return status; ++ + /* FIXME: DSC? */ + return intel_dsi_mode_valid(connector, mode); + } +diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c +index 4a8ff2f976085..e60b2cf84b851 100644 +--- a/drivers/gpu/drm/i915/display/intel_crt.c ++++ b/drivers/gpu/drm/i915/display/intel_crt.c +@@ -343,8 +343,13 @@ intel_crt_mode_valid(struct drm_connector *connector, + struct drm_device *dev = connector->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + int max_dotclk = dev_priv->max_dotclk_freq; ++ enum drm_mode_status status; + int max_clock; + ++ status = intel_cpu_transcoder_mode_valid(dev_priv, mode); ++ if (status != MODE_OK) ++ return status; ++ + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) + return MODE_NO_DBLESCAN; + +diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c +index 96e679a176e94..1777a12f2f421 100644 +--- a/drivers/gpu/drm/i915/display/intel_display.c ++++ b/drivers/gpu/drm/i915/display/intel_display.c +@@ -8229,6 +8229,16 @@ intel_mode_valid(struct drm_device *dev, + mode->vtotal > vtotal_max) + return MODE_V_ILLEGAL; + ++ return MODE_OK; ++} ++ ++enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv, ++ const struct drm_display_mode *mode) ++{ ++ /* ++ * Additional transcoder timing limits, ++ * excluding BXT/GLK DSI transcoders. ++ */ + if (DISPLAY_VER(dev_priv) >= 5) { + if (mode->hdisplay < 64 || + mode->htotal - mode->hdisplay < 32) +diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h +index 884e8e67b17c7..b4f941674357b 100644 +--- a/drivers/gpu/drm/i915/display/intel_display.h ++++ b/drivers/gpu/drm/i915/display/intel_display.h +@@ -554,6 +554,9 @@ enum drm_mode_status + intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, + const struct drm_display_mode *mode, + bool bigjoiner); ++enum drm_mode_status ++intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915, ++ const struct drm_display_mode *mode); + enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); + bool is_trans_port_sync_mode(const struct intel_crtc_state *state); + bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index fd7c360bb44d7..5970f4149090f 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -973,6 +973,10 @@ intel_dp_mode_valid(struct drm_connector *_connector, + enum drm_mode_status status; + bool dsc = false, bigjoiner = false; + ++ status = intel_cpu_transcoder_mode_valid(dev_priv, mode); ++ if (status != MODE_OK) ++ return status; ++ + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_H_ILLEGAL; + +diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c +index 9a6822256ddf6..eec32f682012c 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c ++++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c +@@ -703,6 +703,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, + return 0; + } + ++ *status = intel_cpu_transcoder_mode_valid(dev_priv, mode); ++ if (*status != MODE_OK) ++ return 0; ++ + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { + *status = MODE_NO_DBLESCAN; + return 0; +diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c +index 5572e43026e4d..511c589070087 100644 +--- a/drivers/gpu/drm/i915/display/intel_dvo.c ++++ b/drivers/gpu/drm/i915/display/intel_dvo.c +@@ -225,10 +225,16 @@ intel_dvo_mode_valid(struct drm_connector *connector, + { + struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_dvo *intel_dvo = intel_attached_dvo(intel_connector); ++ struct drm_i915_private *i915 = to_i915(intel_connector->base.dev); + const struct drm_display_mode *fixed_mode = + intel_panel_fixed_mode(intel_connector, mode); + int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int target_clock = mode->clock; ++ enum drm_mode_status status; ++ ++ status = intel_cpu_transcoder_mode_valid(i915, mode); ++ if (status != MODE_OK) ++ return status; + + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) + return MODE_NO_DBLESCAN; +diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c +index 4f31355d09a4e..2600019fc8b96 100644 +--- a/drivers/gpu/drm/i915/display/intel_hdmi.c ++++ b/drivers/gpu/drm/i915/display/intel_hdmi.c +@@ -1987,6 +1987,10 @@ intel_hdmi_mode_valid(struct drm_connector *connector, + bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); + bool ycbcr_420_only; + ++ status = intel_cpu_transcoder_mode_valid(dev_priv, mode); ++ if (status != MODE_OK) ++ return status; ++ + if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) + clock *= 2; + +diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c +index e4606d9a25edb..40b5d3d3c7e14 100644 +--- a/drivers/gpu/drm/i915/display/intel_lvds.c ++++ b/drivers/gpu/drm/i915/display/intel_lvds.c +@@ -389,11 +389,16 @@ intel_lvds_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) + { + struct intel_connector *intel_connector = to_intel_connector(connector); ++ struct drm_i915_private *i915 = to_i915(intel_connector->base.dev); + const struct drm_display_mode *fixed_mode = + intel_panel_fixed_mode(intel_connector, mode); + int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; + enum drm_mode_status status; + ++ status = intel_cpu_transcoder_mode_valid(i915, mode); ++ if (status != MODE_OK) ++ return status; ++ + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) + return MODE_NO_DBLESCAN; + +diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c +index c1a85128911e1..8294dddfd9de8 100644 +--- a/drivers/gpu/drm/i915/display/intel_sdvo.c ++++ b/drivers/gpu/drm/i915/display/intel_sdvo.c +@@ -1873,13 +1873,19 @@ static enum drm_mode_status + intel_sdvo_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) + { ++ struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); + struct intel_sdvo_connector *intel_sdvo_connector = + to_intel_sdvo_connector(connector); +- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); ++ int max_dotclk = i915->max_dotclk_freq; ++ enum drm_mode_status status; + int clock = mode->clock; + ++ status = intel_cpu_transcoder_mode_valid(i915, mode); ++ if (status != MODE_OK) ++ return status; ++ + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) + return MODE_NO_DBLESCAN; + +diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c +index dcf89d701f0f6..fb25be800e753 100644 +--- a/drivers/gpu/drm/i915/display/intel_tv.c ++++ b/drivers/gpu/drm/i915/display/intel_tv.c +@@ -956,8 +956,14 @@ static enum drm_mode_status + intel_tv_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) + { ++ struct drm_i915_private *i915 = to_i915(connector->dev); + const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); +- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; ++ int max_dotclk = i915->max_dotclk_freq; ++ enum drm_mode_status status; ++ ++ status = intel_cpu_transcoder_mode_valid(i915, mode); ++ if (status != MODE_OK) ++ return status; + + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) + return MODE_NO_DBLESCAN; +diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c +index 00c80f29ad999..114088ca59ed4 100644 +--- a/drivers/gpu/drm/i915/display/vlv_dsi.c ++++ b/drivers/gpu/drm/i915/display/vlv_dsi.c +@@ -1627,9 +1627,25 @@ static const struct drm_encoder_funcs intel_dsi_funcs = { + .destroy = intel_dsi_encoder_destroy, + }; + ++static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector, ++ struct drm_display_mode *mode) ++{ ++ struct drm_i915_private *i915 = to_i915(connector->dev); ++ ++ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { ++ enum drm_mode_status status; ++ ++ status = intel_cpu_transcoder_mode_valid(i915, mode); ++ if (status != MODE_OK) ++ return status; ++ } ++ ++ return intel_dsi_mode_valid(connector, mode); ++} ++ + static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { + .get_modes = intel_dsi_get_modes, +- .mode_valid = intel_dsi_mode_valid, ++ .mode_valid = vlv_dsi_mode_valid, + .atomic_check = intel_digital_connector_atomic_check, + }; + +-- +2.42.0 + diff --git a/queue-6.1/series b/queue-6.1/series index d67e272ee3f..bbbe9bf0c24 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -188,3 +188,7 @@ mips-loongson64-handle-more-memory-types-passed-from-firmware.patch mips-loongson64-enable-dma-noncoherent-support.patch netfilter-nft_set_pipapo-skip-inactive-elements-during-set-walk.patch riscv-kconfig-add-select-arm_amba-to-soc_starfive.patch +drm-i915-display-drop-check-for-doublescan-mode-in-m.patch +drm-i915-lvds-use-reg_bit-co.patch +drm-i915-sdvo-stop-caching-has_hdmi_monitor-in-struc.patch +drm-i915-skip-some-timing-checks-on-bxt-glk-dsi-tran.patch -- 2.47.3