From aebea9d20a5aa32857f320c07ca8f9fd1b3dec1f Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 29 Aug 2016 13:01:19 +0530 Subject: [PATCH] spi: xilinx_spi: Correct the fifo-depth calculation Correctly fill the fifo depth by passing correct node in getting it from device tree. This fixes the issue of hanging in a loop while reading environment from spi flash during boot up which is caused by commit "spi: xilinx_spi: Modify transfer logic for quad mode" (sha1: c638e0e80e5ddfac2999692f4aa824021bf3f196) Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/spi/xilinx_spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 7bdf716a154..581cd4dc002 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -343,13 +343,12 @@ static const struct dm_spi_ops xilinx_spi_ops = { static int xilinx_spi_ofdata_to_platdata(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus); - struct udevice *dev = dev_get_parent(bus); priv->regs = (struct xilinx_spi_regs *)dev_get_addr(bus); debug("%s: regs=%p\n", __func__, priv->regs); - priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, bus->of_offset, "fifo-size", 0); return 0; -- 2.47.3