From b421344f419911bf046c1f414ea2b9d25aaa3e97 Mon Sep 17 00:00:00 2001 From: Alice Carlotti Date: Fri, 3 Oct 2025 05:50:44 +0100 Subject: [PATCH] aarch64: Use constant fields in simple_index operands Update aarch64_{ins|ext}_simple_index to use constant fields, and swap the order of the index and regno fields, so that the regno occupies the last five bits. (Splitting/combining a variable length value and a fixed length value is easiest if the fixed length value occupies the least significant bits.) --- opcodes/aarch64-asm.c | 9 +++-- opcodes/aarch64-dis.c | 10 +++--- opcodes/aarch64-opc-2.c | 64 ++++++++++++++++++------------------ opcodes/aarch64-opc.c | 5 +-- opcodes/aarch64-opc.h | 5 +-- opcodes/aarch64-tbl.h | 73 ++++++++++++++++++++++------------------- 6 files changed, 86 insertions(+), 80 deletions(-) diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index c9ffdd2c1a9..21395bb1d0e 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1795,8 +1795,8 @@ aarch64_ins_x0_to_x30 (const aarch64_operand *self, return true; } -/* Insert an indexed register, with the first field being the register - number and the remaining fields being the index. */ +/* Insert an indexed register, with the last five field bits holding the + register number and the remaining bits holding the index. */ bool aarch64_ins_simple_index (const aarch64_operand *self, const aarch64_opnd_info *info, @@ -1804,9 +1804,8 @@ aarch64_ins_simple_index (const aarch64_operand *self, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - int bias = get_operand_specific_data (self); - insert_field (self->fields[0], code, info->reglane.regno - bias, 0); - insert_all_fields_after (self, 1, code, info->reglane.index); + unsigned int val = (info->reglane.index << 5) | info->reglane.regno; + insert_all_fields (self, code, val); return true; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 601199a56e4..2bde0ca7daa 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2440,17 +2440,17 @@ aarch64_ext_x0_to_x30 (const aarch64_operand *self, aarch64_opnd_info *info, return info->reg.regno <= 30; } -/* Decode an indexed register, with the first field being the register - number and the remaining fields being the index. */ +/* Decode an indexed register, with the last five field bits holding the + register number and the remaining bits holding the index. */ bool aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - int bias = get_operand_specific_data (self); - info->reglane.regno = extract_field (self->fields[0], code, 0) + bias; - info->reglane.index = extract_all_fields_after (self, 1, code); + unsigned int val = extract_all_fields (self, code); + info->reglane.regno = val & 31; + info->reglane.index = val >> 5; return true; } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 02f29c0401c..2ce7b00724c 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -65,9 +65,9 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V7"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm1_14}, "a SIMD vector without a type qualifier encoding a bit index"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm2_13}, "a SIMD vector without a type qualifier encoding a bit index"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm3_12}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_14, FLD_Rm}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_13, FLD_Rm}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12, FLD_Rm}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, @@ -264,11 +264,11 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i1_23}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i2}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1_23, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h3, FLD_SVE_i3l2, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"}, @@ -304,8 +304,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_PNd3}, "an SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SVE_Pg3}, "an SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm1_8}, "an indexed SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm2_8}, "an indexed SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_8, FLD_CONST_01, FLD_SME_PNn3}, "an indexed SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_8, FLD_CONST_01, FLD_SME_PNn3}, "an indexed SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off1x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm1_0}, "ZA array"}, @@ -320,32 +320,32 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a shift-right immediate operand"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm1_3}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm1_3}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm2_1}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm2_2}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10, FLD_imm1_3}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm3_10}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_19", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_19}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm1_2, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm2_2, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm3_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_16, FLD_SVE_Zn}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_15, FLD_SVE_Zn}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_16, FLD_SVE_Zn}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_19", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_Zn}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_14, FLD_SVE_Zn}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_15, FLD_SVE_Zn}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_14, FLD_SVE_Zn}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register with option zero index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_1}, "an SVE vector register with optional one bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_2}, "an SVE vector register with optional two bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_1, FLD_SVE_Zn}, "an SVE vector register with optional one bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_2, FLD_SVE_Zn}, "an SVE vector register with optional two bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zn}, "an SVE vector register with optional three bit index"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register with option zero index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_1}, "an SVE vector register with optional one bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_2}, "an SVE vector register with optional two bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_1, FLD_SVE_Zd}, "an SVE vector register with optional one bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_2, FLD_SVE_Zd}, "an SVE vector register with optional two bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zd}, "an SVE vector register with optional three bit index"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index e080707dd15..1050f8ffea6 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -228,6 +228,7 @@ const aarch64_field aarch64_fields[] = AARCH64_FIELD_NIL, /* NIL. */ AARCH64_FIELD_CONST (0, 1), /* CONST_0. */ AARCH64_FIELD_CONST (0, 2), /* CONST_00. */ + AARCH64_FIELD_CONST (1, 2), /* CONST_01. */ AARCH64_FIELD_CONST (1, 1), /* CONST_1. */ AARCH64_FIELD ( 8, 4), /* CRm: in the system instructions. */ AARCH64_FIELD (10, 2), /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */ @@ -1921,7 +1922,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_PNn3_INDEX1: case AARCH64_OPND_SME_PNn3_INDEX2: - size = get_operand_field_width (get_operand_from_code (type), 1); + size = get_operand_field_width (get_operand_from_code (type), 0); if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15, 0, (1 << size) - 1)) return false; @@ -1959,7 +1960,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_Zm_INDEX4_2: case AARCH64_OPND_SME_Zm_INDEX4_3: case AARCH64_OPND_SME_Zm_INDEX4_10: - size = get_operand_fields_width (get_operand_from_code (type)) - 4; + size = get_operand_fields_width (get_operand_from_code (type)) - 5; if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15, 0, (1 << size) - 1)) return false; diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index af0f0d857c0..2e5d2c30850 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -32,6 +32,7 @@ enum aarch64_field_kind FLD_NIL, FLD_CONST_0, FLD_CONST_00, + FLD_CONST_01, FLD_CONST_1, FLD_CRm, FLD_CRm_dsb_nxs, @@ -294,9 +295,9 @@ struct aarch64_operand unsigned int flags; - /* The associated instruction bit-fields; no operand has more than 4 + /* The associated instruction bit-fields; no operand has more than 5 bit-fields */ - enum aarch64_field_kind fields[5]; + enum aarch64_field_kind fields[6]; /* Brief description */ const char *desc; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index bfa235daa8c..86969201b45 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -7564,11 +7564,14 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a SIMD vector element limited to V0-V15") \ Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD_Rm), \ "a SIMD vector element limited to V0-V7") \ - Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, F(FLD_Rm, FLD_imm1_14), \ + Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, \ + F(FLD_imm1_14, FLD_Rm), \ "a SIMD vector without a type qualifier encoding a bit index") \ - Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, F(FLD_Rm, FLD_imm2_13), \ + Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, \ + F(FLD_imm2_13, FLD_Rm), \ "a SIMD vector without a type qualifier encoding a bit index") \ - Y(SIMD_ELEMENT, simple_index, "Em_INDEX3_12", 0, F(FLD_Rm, FLD_imm3_12), \ + Y(SIMD_ELEMENT, simple_index, "Em_INDEX3_12", 0, \ + F(FLD_imm3_12, FLD_Rm), \ "a SIMD vector without a type qualifier encoding a bit index") \ Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ "a SIMD vector register list") \ @@ -7988,10 +7991,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \ "an SVE vector register") \ Y(SVE_REG, simple_index, "SVE_Zm1_23_INDEX", \ - 0, F(FLD_SVE_Zm_16, FLD_SVE_i1_23), \ + 0, F(FLD_SVE_i1_23, FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SVE_Zm2_22_INDEX", \ - 0, F(FLD_SVE_Zm_16, FLD_SVE_i2), \ + 0, F(FLD_SVE_i2, FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ @@ -8000,7 +8003,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SVE_Zm3_12_INDEX", \ - 0, F(FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2), \ + 0, F(FLD_SVE_i3h3, FLD_SVE_i3l2, FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_19_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_imm2_19, FLD_SVE_imm3), \ @@ -8086,11 +8089,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an SVE predicate-as-counter register") \ Y(PRED_REG, regno, "SME_PNn", 0, F(FLD_SVE_Pn), \ "an SVE predicate-as-counter register") \ - Y(SVE_REG, simple_index, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB, \ - F(FLD_SME_PNn3, FLD_imm1_8), \ + Y(SVE_REG, simple_index, "SME_PNn3_INDEX1", 0, \ + F(FLD_imm1_8, FLD_CONST_01, FLD_SME_PNn3), \ "an indexed SVE predicate-as-counter register") \ - Y(SVE_REG, simple_index, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB, \ - F(FLD_SME_PNn3, FLD_imm2_8), \ + Y(SVE_REG, simple_index, "SME_PNn3_INDEX2", 0, \ + F(FLD_imm2_8, FLD_CONST_01, FLD_SME_PNn3), \ "an indexed SVE predicate-as-counter register") \ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \ @@ -8123,71 +8126,73 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \ F(FLD_SVE_tszh,FLD_SVE_imm5b), "a shift-right immediate operand") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \ - F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \ + F(FLD_imm1_10, FLD_CONST_0, FLD_SME_Zm), \ + "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \ - F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \ + F(FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm), \ + "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX2_3", 0, \ - F(FLD_SME_Zm, FLD_imm1_10, FLD_imm1_3), \ + F(FLD_imm1_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_1", 0, \ - F(FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1), \ + F(FLD_imm1_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_2", 0, \ - F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2), \ + F(FLD_imm2_10, FLD_imm1_2, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_3", 0, \ - F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_3), \ + F(FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_10", 0, \ - F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10), \ + F(FLD_imm1_15, FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_1", 0, \ - F(FLD_SME_Zm, FLD_imm2_10, FLD_imm2_1), \ + F(FLD_imm2_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_2", 0, \ - F(FLD_SME_Zm, FLD_imm2_10, FLD_imm2_2), \ + F(FLD_imm2_10, FLD_imm2_2, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_3", 0, \ - F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10, FLD_imm1_3), \ + F(FLD_imm1_15, FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_10", 0, \ - F(FLD_SME_Zm, FLD_imm1_15, FLD_imm3_10), \ + F(FLD_imm1_15, FLD_imm3_10, FLD_CONST_0, FLD_SME_Zm), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \ - F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \ + F(FLD_imm1_16, FLD_SVE_Zn), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \ - F(FLD_SVE_Zn, FLD_imm2_15), "an indexed SVE vector register") \ + F(FLD_imm2_15, FLD_SVE_Zn), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \ - F(FLD_SVE_Zn, FLD_imm2_16), "an indexed SVE vector register") \ + F(FLD_imm2_16, FLD_SVE_Zn), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_19", 0, \ - F(FLD_SVE_Zn, FLD_imm2_19), "an indexed SVE vector register") \ + F(FLD_imm2_19, FLD_SVE_Zn), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \ - F(FLD_SVE_Zn, FLD_imm3_14), "an indexed SVE vector register") \ + F(FLD_imm3_14, FLD_SVE_Zn), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \ - F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \ + F(FLD_imm3_15, FLD_SVE_Zn), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \ - F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \ + F(FLD_imm4_14, FLD_SVE_Zn), "an indexed SVE vector register") \ Y(SVE_REG, regno, "SVE_Zn0_INDEX", 0, F(FLD_SVE_Zn), \ "an SVE vector register with option zero index") \ Y(SVE_REG, simple_index, "SVE_Zn1_17_INDEX", 0, \ - F(FLD_SVE_Zn, FLD_imm17_1), \ + F(FLD_imm17_1, FLD_SVE_Zn), \ "an SVE vector register with optional one bit index") \ Y(SVE_REG, simple_index, "SVE_Zn2_18_INDEX", 0, \ - F(FLD_SVE_Zn, FLD_imm17_2), \ + F(FLD_imm17_2, FLD_SVE_Zn), \ "an SVE vector register with optional two bit index") \ Y(SVE_REG, simple_index, "SVE_Zn3_22_INDEX", 0, \ - F(FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2), \ + F(FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zn), \ "an SVE vector register with optional three bit index") \ Y(SVE_REG, regno, "SVE_Zd0_INDEX", 0, F(FLD_SVE_Zd), \ "an SVE vector register with option zero index") \ Y(SVE_REG, simple_index, "SVE_Zd1_17_INDEX", 0, \ - F(FLD_SVE_Zd, FLD_imm17_1), \ + F(FLD_imm17_1, FLD_SVE_Zd), \ "an SVE vector register with optional one bit index") \ Y(SVE_REG, simple_index, "SVE_Zd2_18_INDEX", 0, \ - F(FLD_SVE_Zd, FLD_imm17_2), \ + F(FLD_imm17_2, FLD_SVE_Zd), \ "an SVE vector register with optional two bit index") \ Y(SVE_REG, simple_index, "SVE_Zd3_22_INDEX", 0, \ - F(FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2), \ + F(FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zd), \ "an SVE vector register with optional three bit index") \ Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \ "VLx2 or VLx4") \ -- 2.47.3