From ba73f8d2ebe4b5fe8163ee5ab806f0e50961ebdf Mon Sep 17 00:00:00 2001 From: Andreas Arnez Date: Tue, 3 Nov 2020 18:17:30 +0100 Subject: [PATCH] Bug 428648 - s390x: Force 12-bit amode for vector loads in isel Similar to Bug 417452, where the instruction selector sometimes attempted to generate vector stores with a 20-bit displacement, the same problem has now been reported with vector loads. The problem is caused in s390_isel_vec_expr_wrk(), where the addressing mode is generated with s390_isel_amode() instead of s390_isel_amode_short(). This is fixed. --- NEWS | 1 + VEX/priv/host_s390_isel.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index 6afb264062..7b9142fc4a 100644 --- a/NEWS +++ b/NEWS @@ -54,6 +54,7 @@ n-i-bz helgrind: If hg_cli__realloc fails, return NULL. 426123 PPC ISA 3.1 support is missing, part 3 427787 Support new faccessat2 linux syscall (439) 428035 drd: Unbreak the musl build +428648 s390_emit_load_mem panics due to 20-bit offset for vector load Release 3.16.1 (?? June 2020) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 2f80dd8504..134f3eb6fe 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -3741,7 +3741,7 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr) /* --------- LOAD --------- */ case Iex_Load: { HReg dst = newVRegV(env); - s390_amode *am = s390_isel_amode(env, expr->Iex.Load.addr); + s390_amode *am = s390_isel_amode_short(env, expr->Iex.Load.addr); if (expr->Iex.Load.end != Iend_BE) goto irreducible; -- 2.47.3