From c4f6267be502cf7fde69acb0c3d8b4bcb175f3a4 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 27 Feb 2014 19:54:56 +0000 Subject: [PATCH] Copy changes from doc/tm.texi to doc/tm.texi.in * doc/tm.texi.in (Condition Code Status): Update documention for relative locations of cc0-setter and cc0-user. From-SVN: r208205 --- gcc/ChangeLog | 5 +++++ gcc/doc/tm.texi.in | 9 +++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 16c499b05d62..60e7d9e950bf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-02-27 H.J. Lu + + * doc/tm.texi.in (Condition Code Status): Update documention for + relative locations of cc0-setter and cc0-user. + 2014-02-27 Jeff Law PR rtl-optimization/52714 diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 50f412cac08d..6dcbde45cf29 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -4484,8 +4484,13 @@ most instructions do not affect it. The latter category includes most RISC machines. The implicit clobbering poses a strong restriction on the placement of -the definition and use of the condition code, which need to be in adjacent -insns for machines using @code{(cc0)}. This can prevent important +the definition and use of the condition code. In the past the definition +and use were always adjacent. However, recent changes to support trapping +arithmatic may result in the definition and user being in different blocks. +Thus, there may be a @code{NOTE_INSN_BASIC_BLOCK} between them. Additionally, +the definition may be the source of exception handling edges. + +These restrictions can prevent important optimizations on some machines. For example, on the IBM RS/6000, there is a delay for taken branches unless the condition code register is set three instructions earlier than the conditional branch. The instruction -- 2.47.3