From c623f127e4c82885ab0d936616d628d37fb081c7 Mon Sep 17 00:00:00 2001
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Date: Thu, 9 Feb 2017 21:16:01 +0530
Subject: [PATCH] arm64: zynqmp: Correct USB bus and ref clock nodes

Currently usb "bus_clk" & "ref_clk" nodes are wrongly mapped.
This patch fixes the USB0/1 bus and ref clock nodes

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 5386fe969f6..c8b18d2695b 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -230,11 +230,11 @@
 };
 
 &usb0 {
-	clocks = <&clkc 32>,  <&clkc 31>;
+	clocks = <&clkc 33>,  <&clkc 31>;
 };
 
 &usb1 {
-	clocks = <&clkc 33>,  <&clkc 36>;
+	clocks = <&clkc 33>,  <&clkc 32>;
 };
 
 &watchdog0 {
-- 
2.47.3