From ca943582f78a8dc78c882e4b7d0a8af4b8cc3612 Mon Sep 17 00:00:00 2001 From: jakub Date: Tue, 5 Apr 2016 08:15:09 +0000 Subject: [PATCH] PR target/70525 * config/i386/sse.md (*andnot3): Simplify assertions. Use vpandn for V16SI/V8DImode, vpandnq for V32HI/V64QImode, don't use , fix up formatting. (*andnot3_mask): Remove insn with VI12_AVX512VL iterator. * gcc.target/i386/pr70525.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234739 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 +++- gcc/config/i386/sse.md | 72 ++++++++++--------------- gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/gcc.target/i386/pr70525.c | 32 +++++++++++ 4 files changed, 75 insertions(+), 44 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr70525.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b97f4ac848fa..c0a8f729505b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2016-04-05 Jakub Jelinek + + PR target/70525 + * config/i386/sse.md (*andnot3): Simplify assertions. + Use vpandn for V16SI/V8DImode, vpandnq for + V32HI/V64QImode, don't use , fix up formatting. + (*andnot3_mask): Remove insn with VI12_AVX512VL iterator. + 2016-04-05 Richard Biener PR middle-end/70499 @@ -9,7 +17,7 @@ PR ipa/66223 * ipa-devirt.c (maybe_record_node): Do not optimize cxa_pure_virtual calls when sanitizing. - (possible_polymorphic_call_target_p)" FIx formating. + (possible_polymorphic_call_target_p): Fix formating. 2016-04-04 Bill Schmidt Jakub Jelinek diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5fd650fde4ac..8e9d5ec7cd9e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -11377,45 +11377,46 @@ case MODE_XI: gcc_assert (TARGET_AVX512F); case MODE_OI: - gcc_assert (TARGET_AVX2 || TARGET_AVX512VL); + gcc_assert (TARGET_AVX2); case MODE_TI: - gcc_assert (TARGET_SSE2 || TARGET_AVX512VL); + gcc_assert (TARGET_SSE2); switch (mode) - { - case V16SImode: - case V8DImode: - if (TARGET_AVX512F) - { - tmp = "pandn"; - break; - } - case V8SImode: - case V4DImode: - case V4SImode: - case V2DImode: - if (TARGET_AVX512VL) - { - tmp = "pandn"; - break; - } - default: - tmp = TARGET_AVX512VL ? "pandnq" : "pandn"; - } + { + case V64QImode: + case V32HImode: + /* There is no vpandnb or vpandnw instruction, nor vpandn for + 512-bit vectors. Use vpandnq instead. */ + tmp = "pandnq"; + break; + case V16SImode: + case V8DImode: + tmp = "pandn"; + break; + case V8SImode: + case V4DImode: + case V4SImode: + case V2DImode: + tmp = TARGET_AVX512VL ? "pandn" : "pandn"; + break; + default: + tmp = TARGET_AVX512VL ? "pandnq" : "pandn"; + break; + } break; - case MODE_V16SF: + case MODE_V16SF: gcc_assert (TARGET_AVX512F); - case MODE_V8SF: + case MODE_V8SF: gcc_assert (TARGET_AVX); - case MODE_V4SF: + case MODE_V4SF: gcc_assert (TARGET_SSE); tmp = "andnps"; break; - default: + default: gcc_unreachable (); - } + } switch (which_alternative) { @@ -11423,7 +11424,7 @@ ops = "%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); @@ -11473,21 +11474,6 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "*andnot3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (and:VI12_AVX512VL - (not:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand" "v")) - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")) - (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C") - (match_operand: 4 "register_operand" "Yk")))] - "TARGET_AVX512BW" - "vpandn\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"; - [(set_attr "type" "sselog") - (set_attr "prefix" "evex") - (set_attr "mode" "")]) - (define_expand "3" [(set (match_operand:VI 0 "register_operand") (any_logic:VI diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index baebdb0a21b8..f3d1a6e69198 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-04-05 Jakub Jelinek + + PR target/70525 + * gcc.target/i386/pr70525.c: New test. + 2016-04-05 Richard Biener PR middle-end/70499 diff --git a/gcc/testsuite/gcc.target/i386/pr70525.c b/gcc/testsuite/gcc.target/i386/pr70525.c new file mode 100644 index 000000000000..78ba752f94b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70525.c @@ -0,0 +1,32 @@ +/* PR target/70525 */ +/* { dg-do assemble { target avx512bw } } */ +/* { dg-options "-O2 -mavx512bw -mno-avx512vl" } */ + +typedef char v64qi __attribute__ ((vector_size (64))); +typedef short v32hi __attribute__ ((vector_size (64))); +typedef int v16si __attribute__ ((vector_size (64))); +typedef long long v8di __attribute__ ((vector_size (64))); + +v64qi +f1 (v64qi x, v64qi y) +{ + return x & ~y; +} + +v32hi +f2 (v32hi x, v32hi y) +{ + return x & ~y; +} + +v16si +f3 (v16si x, v16si y) +{ + return x & ~y; +} + +v8di +f4 (v8di x, v8di y) +{ + return x & ~y; +} -- 2.47.3