From d0263d2d27c1634d50e1686c089e2d6cb61f34ac Mon Sep 17 00:00:00 2001 From: Anurag Kumar Vulisha Date: Fri, 16 Feb 2018 00:58:20 +0530 Subject: [PATCH] dts: xilinx: Correct GT lanes for zcu111 board This patch corrects the GT lanes for zcu111 board Signed-off-by: Anurag Kumar Vulisha Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu111-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index b1d3706f0d9..f5c74e3f68e 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -727,7 +727,7 @@ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; - phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; + phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ @@ -771,7 +771,7 @@ &xlnx_dp { status = "okay"; phy-names = "dp-phy0", "dp-phy1"; - phys = <&lane1 PHY_TYPE_DP 0 3 27000000>, <&lane0 PHY_TYPE_DP 1 3 27000000>; + phys = <&lane1 PHY_TYPE_DP 0 1 27000000>, <&lane0 PHY_TYPE_DP 1 1 27000000>; }; &xlnx_dp_sub { -- 2.47.3