From d49e683574537d416aa0fb022d800430e7c045b6 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 22 Aug 2025 11:26:34 +0200 Subject: [PATCH] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videocc Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8550 platform. Hence add MXC power domain to videocc node on SM8550. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-2-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee59709742558..3c6f524994657 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3307,8 +3307,10 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- 2.47.3