From d59cfe9152b306a0a744a322a6074aeff9bc5ef8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 30 Jul 2015 11:51:34 +0200 Subject: [PATCH] xilinx: Remove all ancient code - Remove PPC code from the tree - Revert LL_Temac driver and use mainline one Signed-off-by: Michal Simek --- board/avnet/fx12mm/Makefile | 11 + board/avnet/fx12mm/fx12mm.c | 34 + board/avnet/fx12mm/xparameters.h | 35 + board/avnet/v5fx30teval/Makefile | 11 + board/avnet/v5fx30teval/v5fx30teval.c | 17 + board/avnet/v5fx30teval/xparameters.h | 22 + board/xilinx/microblaze-generic/config.mk | 18 + .../microblaze-generic/microblaze-generic.c | 42 +- board/xilinx/microblaze-generic/xparameters.h | 67 ++ board/xilinx/ml507/Makefile | 11 + board/xilinx/ml507/ml507.c | 17 + board/xilinx/ml507/xparameters.h | 23 + board/xilinx/ppc405-generic/ppc405-generic.c | 104 --- board/xilinx/ppc405-generic/u-boot.lds | 132 --- board/xilinx/ppc405-generic/xparameters.h | 25 + board/xilinx/ppc440-generic/Makefile | 4 +- board/xilinx/ppc440-generic/ppc440-generic.c | 104 --- board/xilinx/ppc440-generic/u-boot.lds | 104 --- board/xilinx/ppc440-generic/xparameters.h | 23 + drivers/net/Makefile | 3 +- drivers/net/xilinx_ll_temac.c | 880 ++++++------------ drivers/net/xilinx_ll_temac.h | 307 ++++++ drivers/net/xilinx_ll_temac_fifo.c | 139 +++ drivers/net/xilinx_ll_temac_fifo.h | 118 +++ drivers/net/xilinx_ll_temac_mdio.c | 177 ++++ drivers/net/xilinx_ll_temac_mdio.h | 50 + drivers/net/xilinx_ll_temac_sdma.c | 366 ++++++++ drivers/net/xilinx_ll_temac_sdma.h | 277 ++++++ include/configs/fx12mm.h | 51 + include/configs/ml507.h | 39 + include/configs/v5fx30teval.h | 39 + include/configs/xilinx-ppc405-generic.h | 303 +----- include/configs/xilinx-ppc405.h | 22 + include/configs/xilinx-ppc440-generic.h | 295 +----- include/netdev.h | 4 +- 35 files changed, 2258 insertions(+), 1616 deletions(-) create mode 100644 board/avnet/fx12mm/Makefile create mode 100644 board/avnet/fx12mm/fx12mm.c create mode 100644 board/avnet/fx12mm/xparameters.h create mode 100644 board/avnet/v5fx30teval/Makefile create mode 100644 board/avnet/v5fx30teval/v5fx30teval.c create mode 100644 board/avnet/v5fx30teval/xparameters.h create mode 100644 board/xilinx/microblaze-generic/config.mk create mode 100644 board/xilinx/microblaze-generic/xparameters.h create mode 100644 board/xilinx/ml507/Makefile create mode 100644 board/xilinx/ml507/ml507.c create mode 100644 board/xilinx/ml507/xparameters.h delete mode 100644 board/xilinx/ppc405-generic/ppc405-generic.c delete mode 100644 board/xilinx/ppc405-generic/u-boot.lds create mode 100644 board/xilinx/ppc405-generic/xparameters.h delete mode 100644 board/xilinx/ppc440-generic/ppc440-generic.c delete mode 100644 board/xilinx/ppc440-generic/u-boot.lds create mode 100644 board/xilinx/ppc440-generic/xparameters.h create mode 100644 drivers/net/xilinx_ll_temac.h create mode 100644 drivers/net/xilinx_ll_temac_fifo.c create mode 100644 drivers/net/xilinx_ll_temac_fifo.h create mode 100644 drivers/net/xilinx_ll_temac_mdio.c create mode 100644 drivers/net/xilinx_ll_temac_mdio.h create mode 100644 drivers/net/xilinx_ll_temac_sdma.c create mode 100644 drivers/net/xilinx_ll_temac_sdma.h create mode 100644 include/configs/fx12mm.h create mode 100644 include/configs/ml507.h create mode 100644 include/configs/v5fx30teval.h create mode 100644 include/configs/xilinx-ppc405.h diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile new file mode 100644 index 00000000000..618b42f8917 --- /dev/null +++ b/board/avnet/fx12mm/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es +# This work has been supported by: Qtechnology http://qtec.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += fx12mm.o + +include $(srctree)/board/xilinx/ppc405-generic/Makefile diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c new file mode 100644 index 00000000000..92e1cfb75f3 --- /dev/null +++ b/board/avnet/fx12mm/fx12mm.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2008 + * + * Author: Xilinx Inc. + * + * Modified by: + * Georg Schardt + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int checkboard(void) +{ + char buf[64]; + int i; + int l = getenv_f("serial#", buf, sizeof(buf)); + + if (l < 0) { + printf("Avnet Virtex4 FX12 with no serial #"); + } else { + printf("Avnet Virtex4 FX12 Minimodul # "); + for (i = 0; i < l; ++i) { + if (buf[i] == ' ') + break; + putc(buf[i]); + } + } + putc('\n'); + return 0; +} diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h new file mode 100644 index 00000000000..94f682f8ecc --- /dev/null +++ b/board/avnet/fx12mm/xparameters.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2008 + * + * Georg Schardt + * + * SPDX-License-Identifier: GPL-2.0+ + * + * CAUTION: This file is based on the xparameters.h automatically + * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5 + */ + +#ifndef __XPARAMETER_H__ +#define __XPARAMETER_H__ + +/* RS232 */ +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 +#define XPAR_UARTNS550_0_BASEADDR 0x83E00000 + + +/* INT_C */ +#define XPAR_XPS_INTC_0_DEVICE_ID 0 +#define XPAR_XPS_INTC_0_BASEADDR 0x81800000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 + +/* CPU core clock */ +#define XPAR_CORE_CLOCK_FREQ_HZ 300000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 + +/* RAM */ +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 + +/* FLASH */ +#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 + +#endif diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile new file mode 100644 index 00000000000..8c41af02d4f --- /dev/null +++ b/board/avnet/v5fx30teval/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es +# This work has been supported by: Qtechnology http://qtec.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += v5fx30teval.o + +include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c new file mode 100644 index 00000000000..68b0eb959de --- /dev/null +++ b/board/avnet/v5fx30teval/v5fx30teval.c @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#include +#include +#include + + +int checkboard(void) +{ + puts("Avnet Virtex 5 FX30 Evaluation Board\n"); + return 0; +} diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h new file mode 100644 index 00000000000..95b8c285ad1 --- /dev/null +++ b/board/avnet/v5fx30teval/xparameters.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk new file mode 100644 index 00000000000..36bdd963434 --- /dev/null +++ b/board/xilinx/microblaze-generic/config.mk @@ -0,0 +1,18 @@ +# +# (C) Copyright 2007 Michal Simek +# +# Michal SIMEK +# +# SPDX-License-Identifier: GPL-2.0+ +# +# CAUTION: This file is a faked configuration !!! +# There is no real target for the microblaze-generic +# configuration. You have to replace this file with +# the generated file from your Xilinx design flow. +# + +CONFIG_SYS_TEXT_BASE = 0x29000000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 690c5700031..375cd0b6feb 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -121,19 +121,41 @@ int board_eth_init(bd_t *bis) ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, txpp, rxpp); #endif + #ifdef CONFIG_XILINX_LL_TEMAC -# ifdef XILINX_LLTEMAC_FIFO_BASEADDR - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 0, - XILINX_LLTEMAC_FIFO_BASEADDR); -# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR -# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 3, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# else - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 1, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); +# ifdef XILINX_LLTEMAC_BASEADDR +# ifdef XILINX_LLTEMAC_FIFO_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR); +# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR +# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); +# else + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_PLB, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); +# endif +# endif +# endif +# ifdef XILINX_LLTEMAC_BASEADDR1 +# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1); +# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 +# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_SDMA_DCR, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); +# else + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_SDMA_PLB, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); +# endif # endif # endif #endif + return ret; } diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h new file mode 100644 index 00000000000..d6d0d679e8e --- /dev/null +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * SPDX-License-Identifier: GPL-2.0+ + * + * CAUTION: This file is a faked configuration !!! + * There is no real target for the microblaze-generic + * configuration. You have to replace this file with + * the generated file from your Xilinx design flow. + */ + +#define XILINX_BOARD_NAME microblaze-generic + +/* System Clock Frequency */ +#define XILINX_CLOCK_FREQ 100000000 + +/* Microblaze is microblaze_0 */ +#define XILINX_USE_MSR_INSTR 1 +#define XILINX_FSL_NUMBER 3 + +/* Interrupt controller is opb_intc_0 */ +#define XILINX_INTC_BASEADDR 0x41200000 +#define XILINX_INTC_NUM_INTR_INPUTS 6 + +/* Timer pheriphery is opb_timer_1 */ +#define XILINX_TIMER_BASEADDR 0x41c00000 +#define XILINX_TIMER_IRQ 0 + +/* Uart pheriphery is RS232_Uart */ +#define XILINX_UARTLITE_BASEADDR 0x40600000 +#define XILINX_UARTLITE_BAUDRATE 115200 + +/* IIC pheriphery is IIC_EEPROM */ +#define XILINX_IIC_0_BASEADDR 0x40800000 +#define XILINX_IIC_0_FREQ 100000 +#define XILINX_IIC_0_BIT 0 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 + +/* Flash Memory is FLASH_2Mx32 */ +#define XILINX_FLASH_START 0x2c000000 +#define XILINX_FLASH_SIZE 0x00800000 + +/* Main Memory is DDR_SDRAM_64Mx32 */ +#define XILINX_RAM_START 0x28000000 +#define XILINX_RAM_SIZE 0x04000000 + +/* Sysace Controller is SysACE_CompactFlash */ +#define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180ffff +#define XILINX_SYSACE_MEM_WIDTH 16 + +/* Ethernet controller is Ethernet_MAC */ +#define XILINX_EMACLITE_BASEADDR 0x40C00000 + +/* LL_TEMAC Ethernet controller */ +#define XILINX_LLTEMAC_BASEADDR 0x44000000 +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 +#define XILINX_LLTEMAC_BASEADDR1 0x44200000 +#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 + +/* Watchdog IP is wxi_timebase_wdt_0 */ +#define XILINX_WATCHDOG_BASEADDR 0x50000000 +#define XILINX_WATCHDOG_IRQ 1 diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile new file mode 100644 index 00000000000..9a3809f3c06 --- /dev/null +++ b/board/xilinx/ml507/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es +# This work has been supported by: Qtechnology http://qtec.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ml507.o + +include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c new file mode 100644 index 00000000000..83b764b7337 --- /dev/null +++ b/board/xilinx/ml507/ml507.c @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#include +#include +#include + + +int checkboard(void) +{ + puts("Xilinx ML507 Board\n"); + return 0; +} diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h new file mode 100644 index 00000000000..e30e592bbe1 --- /dev/null +++ b/board/xilinx/ml507/xparameters.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif diff --git a/board/xilinx/ppc405-generic/ppc405-generic.c b/board/xilinx/ppc405-generic/ppc405-generic.c deleted file mode 100644 index 31e635c9a62..00000000000 --- a/board/xilinx/ppc405-generic/ppc405-generic.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This is a board specific file. It's OK to include board specific - * header files */ - -#include -#include -#include - -ulong __get_PCI_freq(void) -{ - return 0; -} - -ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); - -phys_size_t __initdram(int board_type) -{ - return get_ram_size(XILINX_RAM_START, XILINX_RAM_SIZE); -} -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); - -void __get_sys_info(sys_info_t *sysInfo) -{ - /* FIXME */ - sysInfo->freqProcessor = XILINX_CLOCK_FREQ; - sysInfo->freqPLB = XILINX_CLOCK_FREQ; - sysInfo->freqPCI = 0; - - return; -} - -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); - -int __checkboard(void) -{ - puts(__stringify(XILINX_BOARD_NAME) "\n"); - return 0; -} -int checkboard(void) __attribute__((weak, alias("__checkboard"))); - - -int gpio_init (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF; -#endif - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif -#ifdef CONFIG_XILINX_LL_TEMAC -# ifdef XILINX_LLTEMAC_FIFO_BASEADDR - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 0, - XILINX_LLTEMAC_FIFO_BASEADDR); -# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR -# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 3, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# else - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 1, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# endif -# endif -#endif - return ret; -} diff --git a/board/xilinx/ppc405-generic/u-boot.lds b/board/xilinx/ppc405-generic/u-boot.lds deleted file mode 100644 index 7fbbca66998..00000000000 --- a/board/xilinx/ppc405-generic/u-boot.lds +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -ENTRY(_start) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - . = ALIGN(4); - .u_boot_list : { - #include - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end__ = .; - ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h new file mode 100644 index 00000000000..f0ff78fca56 --- /dev/null +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_SPI_0_BASEADDR 0x83400000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_SPI_0_NUM_TRANSFER_BITS 8 + +#endif diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index eba71c75470..0acd95d6e4e 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -9,5 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ppc440-generic.o -extra-y += init.o +obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o +extra-y += ../../xilinx/ppc440-generic/init.o diff --git a/board/xilinx/ppc440-generic/ppc440-generic.c b/board/xilinx/ppc440-generic/ppc440-generic.c deleted file mode 100644 index b7cd251938e..00000000000 --- a/board/xilinx/ppc440-generic/ppc440-generic.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This is a board specific file. It's OK to include board specific - * header files */ - -#include -#include -#include - -ulong __get_PCI_freq(void) -{ - return 0; -} - -ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); - -phys_size_t __initdram(int board_type) -{ - return get_ram_size(XILINX_RAM_START, XILINX_RAM_SIZE); -} -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); - -void __get_sys_info(sys_info_t *sysInfo) -{ - /* FIXME */ - sysInfo->freqProcessor = XILINX_CLOCK_FREQ; - sysInfo->freqPLB = XILINX_CLOCK_FREQ; - sysInfo->freqPCI = 0; - - return; -} - -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); - -int __checkboard(void) -{ - /*puts(__stringify(XILINX_BOARD_NAME) "\n");*/ - return 0; -} -int checkboard(void) __attribute__((weak, alias("__checkboard"))); - - -int gpio_init (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF; -#endif - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif -#ifdef CONFIG_XILINX_LL_TEMAC -# ifdef XILINX_LLTEMAC_FIFO_BASEADDR - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 0, - XILINX_LLTEMAC_FIFO_BASEADDR); -# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR -# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 3, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# else - ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR, 1, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# endif -# endif -#endif - return ret; -} diff --git a/board/xilinx/ppc440-generic/u-boot.lds b/board/xilinx/ppc440-generic/u-boot.lds deleted file mode 100644 index 023324dc8ef..00000000000 --- a/board/xilinx/ppc440-generic/u-boot.lds +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -ENTRY(_start_440) - - -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - *(.text*) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - . = ALIGN(4); - .u_boot_list : { - #include - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - } :bss - . = ALIGN(4); - __bss_end__ = .; - ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); - - PROVIDE (end = .); -} diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h new file mode 100644 index 00000000000..e30e592bbe1 --- /dev/null +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 01dada68150..150470c24b0 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -65,7 +65,8 @@ obj-$(CONFIG_ULI526X) += uli526x.o obj-$(CONFIG_VSC7385_ENET) += vsc7385.o obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o -obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o +obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ + xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c index f10c34dfd4c..7cc86571e49 100644 --- a/drivers/net/xilinx_ll_temac.c +++ b/drivers/net/xilinx_ll_temac.c @@ -1,6 +1,9 @@ /* * Xilinx xps_ll_temac ethernet driver for u-boot * + * supports SDMA or FIFO access and MDIO bus communication + * + * Copyright (C) 2011 - 2012 Stephan Linz * Copyright (C) 2008 - 2011 Michal Simek * Copyright (C) 2008 - 2011 PetaLogix * @@ -9,653 +12,224 @@ * March 2008 created * * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf */ #include #include #include +#include #include -#include #include -#include #include -#undef ETH_HALTING - -#define XTE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ -/* XTE_EMCFG_LINKSPD_MASK */ -#define XTE_EMMC_LINKSPD_10 0x00000000 /* for 10 Mbit */ -#define XTE_EMMC_LINKSPD_100 0x40000000 /* for 100 Mbit */ -#define XTE_EMMC_LINKSPD_1000 0x80000000 /* forr 1000 Mbit */ - -#define XTE_RSE_MIIM_RR_MASK 0x0002 -#define XTE_RSE_MIIM_WR_MASK 0x0004 -#define XTE_RSE_CFG_RR_MASK 0x0020 -#define XTE_RSE_CFG_WR_MASK 0x0040 - -/* XPS_LL_TEMAC indirect registers offset definition */ -#define RCW1 0x240 -#define TC 0x280 -#define EMMC 0x300 -#define MC 0x340 -#define UAW0 0x380 -#define UAW1 0x384 -#define AFM 0x390 -#define MIIMWD 0x3b0 -#define MIIMAI 0x3b4 - -#define CNTLREG_WRITE_ENABLE_MASK 0x8000 - -#define MDIO_ENABLE_MASK 0x40 -#define MDIO_CLOCK_DIV_100MHz 0x28 - -/* XPS_LL_TEMAC SDMA registers definition */ -#define TX_CURDESC_PTR 0x03 -#define TX_TAILDESC_PTR 0x04 -#define TX_CHNL_CTRL 0x05 -#define TX_IRQ_REG 0x06 -#define TX_CHNL_STS 0x07 -#define RX_NXTDESC_PTR 0x08 -#define RX_CURDESC_PTR 0x0b -#define RX_TAILDESC_PTR 0x0c -#define RX_CHNL_CTRL 0x0d -#define RX_IRQ_REG 0x0e -#define RX_CHNL_STS 0x0f -#define DMA_CONTROL_REG 0x10 - -/* DMA control bit */ -#define DMA_CONTROL_RESET 0x1 - -/* CDMAC descriptor status bit definitions */ -# define BDSTAT_STOP_ON_END_MASK 0x20 -# define BDSTAT_COMPLETED_MASK 0x10 -# define BDSTAT_SOP_MASK 0x08 -# define BDSTAT_EOP_MASK 0x04 - -# define CHNL_STS_ERROR_MASK 0x80 - -/* All interrupt enable bits */ -#define XLLDMA_CR_IRQ_ALL_EN_MASK 0x00000087 -/* All interrupt bits */ -#define XLLDMA_IRQ_ALL_MASK 0x0000001F -/* Disable error when 2 or 4 bit coalesce counter overflows */ -#define XLLDMA_DMACR_RX_OVERFLOW_ERR_DIS_MASK 0x00000010 -/* Disable error when 2 or 4 bit coalesce counter overflows */ -#define XLLDMA_DMACR_TX_OVERFLOW_ERR_DIS_MASK 0x00000008 -/* Enable use of tail pointer register */ -#define XLLDMA_DMACR_TAIL_PTR_EN_MASK 0x00000004 - -#define LL_FIFO_ISR_RC_COMPLETE 0x04000000 - -#define SDMA_BIT 1 -#define DCR_BIT 2 - -#define DMAALIGN 32 - -/* SDMA Buffer Descriptor */ -struct cdmac_bd_t { - struct cdmac_bd_t *next_p; - unsigned char *phys_buf_p; - unsigned long buf_len; - unsigned char stat; - unsigned char app1_1; - unsigned short app1_2; - unsigned long app2; - unsigned long app3; - unsigned long app4; - unsigned long app5; -}; - -static struct cdmac_bd_t tx_bd __attribute((aligned(DMAALIGN))); -static struct cdmac_bd_t rx_bd __attribute((aligned(DMAALIGN))); - -struct ll_fifo_s { - u32 isr; /* Interrupt Status Register 0x0 */ - u32 ier; /* Interrupt Enable Register 0x4 */ - u32 tdfr; /* Transmit data FIFO reset 0x8 */ - u32 tdfv; /* Transmit data FIFO Vacancy 0xC */ - u32 tdfd; /* Transmit data FIFO 32bit wide data write port 0x10 */ - u32 tlf; /* Write Transmit Length FIFO 0x14 */ - u32 rdfr; /* Read Receive data FIFO reset 0x18 */ - u32 rdfo; /* Receive data FIFO Occupancy 0x1C */ - u32 rdfd; /* Read Receive data FIFO 32bit wide data read port 0x20 */ - u32 rlf; /* Read Receive Length FIFO 0x24 */ - u32 llr; /* Read LocalLink reset 0x28 */ -}; - -static u8 tx_buffer[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); -static u8 rx_buffer[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_fifo.h" +#include "xilinx_ll_temac_sdma.h" +#include "xilinx_ll_temac_mdio.h" -struct temac_reg { - u32 reserved[8]; - u32 msw; /* Hard TEMAC MSW Data Register */ - u32 lsw; /* Hard TEMAC LSW Data Register */ - u32 ctl; /* Hard TEMAC Control Register */ - u32 rdy; /* Hard TEMAC Ready Status */ -}; - -struct ll_priv { - u32 ctrl; - u32 mode; - int phyaddr; - - struct phy_device *phydev; - struct mii_dev *bus; -}; - -#define XILINX_INDIRECT_DCR_ADDRESS_REG 0 -#define XILINX_INDIRECT_DCR_ACCESS_REG 1 - -static void mtdcr_local(u32 reg, u32 val) -{ -#if defined(CONFIG_XILINX_440) - mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, reg); - mtdcr(XILINX_INDIRECT_DCR_ACCESS_REG, val); +#if !defined(CONFIG_MII) +# error "LL_TEMAC requires MII -- missing CONFIG_MII" #endif -} -static u32 mfdcr_local(u32 reg) -{ - u32 val = 0; -#if defined(CONFIG_XILINX_440) - mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, reg); - val = mfdcr(XILINX_INDIRECT_DCR_ACCESS_REG); +#if !defined(CONFIG_PHYLIB) +# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB" #endif - return val; -} - -static void sdma_out_be32(struct ll_priv *priv, u32 offset, u32 val) -{ - if (priv->mode & DCR_BIT) - mtdcr_local(priv->ctrl + offset, val); - else - out_be32((u32 *)(priv->ctrl + offset * 4), val); -} -static u32 sdma_in_be32(struct ll_priv *priv, u32 offset) -{ - if (priv->mode & DCR_BIT) - return mfdcr_local(priv->ctrl + offset); - - return in_be32((u32 *)(priv->ctrl + offset * 4)); -} +struct ll_temac_info { + int flags; + unsigned long base_addr; + unsigned long ctrl_addr; + char *devname; + unsigned int phyaddr; + char *mdio_busname; +}; -static void xps_ll_temac_check_status(struct temac_reg *regs, int mask) +/* Ethernet interface ready status */ +int ll_temac_check_status(struct temac_reg *regs, u32 mask) { - u32 timeout = 2000; + unsigned timeout = 50; /* 1usec * 50 = 50usec */ + /* + * Quote from LL TEMAC documentation: The bits in the RDY + * register are asserted when there is no access in progress. + * When an access is in progress, a bit corresponding to the + * type of access is automatically de-asserted. The bit is + * automatically re-asserted when the access is complete. + */ while (timeout && (!(in_be32(®s->rdy) & mask))) { timeout--; udelay(1); } - if (!timeout) - printf("%s: Timeout\n", __func__); -} - -/* undirect hostif write to ll_temac */ -static void xps_ll_temac_hostif_set(struct eth_device *dev, int emac, - int phy_addr, int reg_addr, int phy_data) -{ - struct temac_reg *regs = (struct temac_reg *)dev->iobase; + if (!timeout) { + printf("%s: Timeout on 0x%08x @%p\n", __func__, + mask, ®s->rdy); + return 1; + } - out_be32(®s->lsw, phy_data); - out_be32(®s->ctl, CNTLREG_WRITE_ENABLE_MASK | MIIMWD); - out_be32(®s->lsw, (phy_addr << 5) | reg_addr); - out_be32(®s->ctl, CNTLREG_WRITE_ENABLE_MASK | MIIMAI | (emac << 10)); - xps_ll_temac_check_status(regs, XTE_RSE_MIIM_WR_MASK); + return 0; } -/* undirect hostif read from ll_temac */ -static unsigned int xps_ll_temac_hostif_get(struct eth_device *dev, - int emac, int phy_addr, int reg_addr) +/* + * Indirect write to ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 23, second paragraph, The use of CTL0 register or CTL1 register + */ +int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data) { - struct temac_reg *regs = (struct temac_reg *)dev->iobase; - - out_be32(®s->lsw, (phy_addr << 5) | reg_addr); - out_be32(®s->ctl, MIIMAI | (emac << 10)); - xps_ll_temac_check_status(regs, XTE_RSE_MIIM_RR_MASK); - return in_be32(®s->lsw); -} + out_be32(®s->lsw, (reg_data & MLSW_MASK)); + out_be32(®s->ctl, CTL_WEN | (regn & CTL_ADDR_MASK)); -/* undirect write to ll_temac */ -static void xps_ll_temac_indirect_set(struct eth_device *dev, - int emac, int reg_offset, int reg_data) -{ - struct temac_reg *regs = (struct temac_reg *)dev->iobase; + if (ll_temac_check_status(regs, RSE_CFG_WR)) + return 0; - out_be32(®s->lsw, reg_data); - out_be32(®s->ctl, - CNTLREG_WRITE_ENABLE_MASK | (emac << 10) | reg_offset); - xps_ll_temac_check_status(regs, XTE_RSE_CFG_WR_MASK); + return 1; } -/* undirect read from ll_temac */ -static int xps_ll_temac_indirect_get(struct eth_device *dev, - int emac, int reg_offset) +/* + * Indirect read from ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 23, second paragraph, The use of CTL0 register or CTL1 register + */ +int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data) { - struct temac_reg *regs = (struct temac_reg *)dev->iobase; + out_be32(®s->ctl, (regn & CTL_ADDR_MASK)); - out_be32(®s->ctl, (emac << 10) | reg_offset); - xps_ll_temac_check_status(regs, XTE_RSE_CFG_RR_MASK); - return in_be32(®s->lsw); + if (ll_temac_check_status(regs, RSE_CFG_RR)) + return 0; + + *reg_data = in_be32(®s->lsw) & MLSW_MASK; + return 1; } -#ifdef DEBUG -/* read from phy */ -static void read_phy_reg(struct eth_device *dev, int phy_addr) +/* setting sub-controller and ll_temac to proper setting */ +static int ll_temac_setup_ctrl(struct eth_device *dev) { - int j, result; + struct ll_temac *ll_temac = dev->priv; + struct temac_reg *regs = (struct temac_reg *)dev->iobase; - debug("phy%d ", phy_addr); - for (j = 0; j < 32; j++) { - result = xps_ll_temac_hostif_get(dev, 0, phy_addr, j); - debug("%d: 0x%x ", j, result); - } - debug("\n"); -} -#endif + if (ll_temac->ctrlreset && ll_temac->ctrlreset(dev)) + return 0; -static void phy_detection(struct eth_device *dev) -{ + if (ll_temac->ctrlinit && ll_temac->ctrlinit(dev)) + return 0; - int i; - struct ll_priv *priv = dev->priv; - unsigned int phyreg = 0; + /* Promiscuous mode disable */ + if (!ll_temac_indirect_set(regs, TEMAC_AFM, 0)) + return 0; + /* Enable Receiver - RX bit */ + if (!ll_temac_indirect_set(regs, TEMAC_RCW1, RCW1_RX)) + return 0; - if (priv->phyaddr != -1 ) { - phyreg = xps_ll_temac_hostif_get(dev, 0, priv->phyaddr, 1); - if ((phyreg & 0x0ffff) != 0x0ffff) { - /* Found a valid PHY address */ - debug("Default phy address %d is valid\n", priv->phyaddr); - } else { - debug("PHY address is not setup correctly %d\n", priv->phyaddr); - priv->phyaddr = -1; - } - } + /* Enable Transmitter - TX bit */ + if (!ll_temac_indirect_set(regs, TEMAC_TC, TC_TX)) + return 0; - /* try out if have ever found the right phy? */ - if (priv->phyaddr == -1) { - for (i = 31; i >= 0; i--) { - phyreg = xps_ll_temac_hostif_get(dev, 0, i, 1); - if ((phyreg & 0x0ffff) != 0x0ffff) { - debug("phy %x result %x\n", i, phyreg); - priv->phyaddr = i; - break; - } - } - } + return 1; } -/* setting ll_temac and phy to proper setting */ -static int xps_ll_temac_phy_ctrl(struct eth_device *dev) +/* + * Configure ll_temac based on negotiated speed and duplex + * reported by PHY handling code + */ +static int ll_temac_adjust_link(struct eth_device *dev) { -#ifdef CONFIG_PHYLIB - unsigned int temp, speed; - struct ll_priv *priv = dev->priv; - struct phy_device *phydev; - - u32 supported = SUPPORTED_10baseT_Half | - SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | - SUPPORTED_100baseT_Full | - SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full; - - phy_detection(dev); - - /* interface - look at tsec */ - phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); + unsigned int speed, emmc_reg; + struct temac_reg *regs = (struct temac_reg *)dev->iobase; + struct ll_temac *ll_temac = dev->priv; + struct phy_device *phydev = ll_temac->phydev; - phydev->supported &= supported; - phydev->advertising = phydev->supported; - priv->phydev = phydev; - phy_config(phydev); - phy_startup(phydev); + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } switch (phydev->speed) { case 1000: - speed = XTE_EMMC_LINKSPD_1000; + speed = EMMC_LSPD_1000; break; case 100: - speed = XTE_EMMC_LINKSPD_100; + speed = EMMC_LSPD_100; break; case 10: - speed = XTE_EMMC_LINKSPD_10; + speed = EMMC_LSPD_10; break; default: return 0; } - temp = xps_ll_temac_indirect_get(dev, 0, EMMC); - temp &= ~XTE_EMMC_LINKSPEED_MASK; - temp |= speed; - xps_ll_temac_indirect_set(dev, 0, EMMC, temp); - - return 1; - -#else - int i; - unsigned int result; - struct ll_priv *priv = dev->priv; - unsigned retries = 10; - unsigned int phyreg = 0; - - phy_detection(dev); - -#ifdef DEBUG - read_phy_reg(dev, priv->phyaddr); -#endif - - /* wait for link up */ - puts("Waiting for link ... "); - retries = 20000; - while (retries-- && - ((xps_ll_temac_hostif_get(dev, 0, priv->phyaddr, 1) - & 0x04) != 0x04)) { - udelay(100); - } - - phyreg = xps_ll_temac_indirect_get(dev, 0, EMMC) & - (~XTE_EMMC_LINKSPEED_MASK); - - /* get PHY id */ - i = (xps_ll_temac_hostif_get(dev, 0, priv->phyaddr, 2) << 16) | - xps_ll_temac_hostif_get(dev, 0, priv->phyaddr, 3); - debug("LL_TEMAC: Phy ID 0x%x\n", i); - - /* FIXME this part will be replaced by PHY lib */ - /* s3e boards */ - if (i == 0x7c0a3) { - /* 100BASE-T/FD */ - xps_ll_temac_indirect_set(dev, 0, EMMC, - (phyreg | XTE_EMMC_LINKSPD_100)); - return 1; - } - -#if 0 - /* Support for Xilinx 1000BASE-X PCS/PMA core */ - if (i == 0x0) { - /* 1000BASE-X/FD */ - xps_ll_temac_indirect_set(dev, 0, EMMC, 0x80000000); - /* Clear the Isolate bit from PHY control register */ - xps_ll_temac_hostif_set(dev, 0, phy_addr, 0, 0x1140); - link = 1; - return 1; - } -#endif - - result = xps_ll_temac_hostif_get(dev, 0, priv->phyaddr, 5); - if ((result & 0x8000) == 0x8000) { - xps_ll_temac_indirect_set(dev, 0, EMMC, - (phyreg | XTE_EMMC_LINKSPD_1000)); - printf("1000BASE-T/FD\n"); - } else if ((result & 0x4000) == 0x4000) { - xps_ll_temac_indirect_set(dev, 0, EMMC, - (phyreg | XTE_EMMC_LINKSPD_100)); - printf("100BASE-T/FD\n"); - } else { - /* unsupported mode or auto-negotiation failed */ - puts("Unsupported mode or auto-negotiation failed\n"); - } - - return 1; -#endif -} - -static inline int xps_ll_temac_dma_error(struct eth_device *dev) -{ - int err; - struct ll_priv *priv = dev->priv; - - /* Check for TX and RX channel errrors. */ - err = sdma_in_be32(priv, TX_CHNL_STS) & CHNL_STS_ERROR_MASK; - err |= sdma_in_be32(priv, RX_CHNL_STS) & CHNL_STS_ERROR_MASK; - return err; -} - -static void xps_ll_temac_reset_dma(struct eth_device *dev) -{ - u32 r; - struct ll_priv *priv = dev->priv; - - /* Soft reset the DMA. */ - sdma_out_be32(priv, DMA_CONTROL_REG, DMA_CONTROL_RESET); - while (sdma_in_be32(priv, DMA_CONTROL_REG) & DMA_CONTROL_RESET) - ; - - /* Now clear the interrupts. */ - r = sdma_in_be32(priv, TX_CHNL_CTRL); - r &= ~XLLDMA_CR_IRQ_ALL_EN_MASK; - sdma_out_be32(priv, TX_CHNL_CTRL, r); - - r = sdma_in_be32(priv, RX_CHNL_CTRL); - r &= ~XLLDMA_CR_IRQ_ALL_EN_MASK; - sdma_out_be32(priv, RX_CHNL_CTRL, r); - - /* Now ACK pending IRQs. */ - sdma_out_be32(priv, TX_IRQ_REG, XLLDMA_IRQ_ALL_MASK); - sdma_out_be32(priv, RX_IRQ_REG, XLLDMA_IRQ_ALL_MASK); - - /* Set tail-ptr mode, disable errors for both channels. */ - sdma_out_be32(priv, DMA_CONTROL_REG, - XLLDMA_DMACR_TAIL_PTR_EN_MASK | - XLLDMA_DMACR_RX_OVERFLOW_ERR_DIS_MASK | - XLLDMA_DMACR_TX_OVERFLOW_ERR_DIS_MASK); -} - -/* bd init */ -static void xps_ll_temac_bd_init(struct eth_device *dev) -{ - struct ll_priv *priv = dev->priv; - - memset(&tx_bd, 0, sizeof(tx_bd)); - memset(&rx_bd, 0, sizeof(rx_bd)); - - rx_bd.phys_buf_p = rx_buffer; - rx_bd.next_p = &rx_bd; - rx_bd.buf_len = PKTSIZE_ALIGN; - flush_cache((u32)&rx_bd, sizeof(tx_bd)); - flush_cache((u32)rx_bd.phys_buf_p, PKTSIZE_ALIGN); - - sdma_out_be32(priv, RX_CURDESC_PTR, (u32)&rx_bd); - sdma_out_be32(priv, RX_TAILDESC_PTR, (u32)&rx_bd); - sdma_out_be32(priv, RX_NXTDESC_PTR, (u32)&rx_bd); /* setup first fd */ - - tx_bd.phys_buf_p = tx_buffer; - tx_bd.next_p = &tx_bd; - - flush_cache((u32)&tx_bd, sizeof(tx_bd)); - sdma_out_be32(priv, TX_CURDESC_PTR, (u32)&tx_bd); -} - -static int ll_temac_send_sdma(struct eth_device *dev, - void *buffer, int length) -{ - struct ll_priv *priv = dev->priv; - - if (xps_ll_temac_dma_error(dev)) { - xps_ll_temac_reset_dma(dev); - xps_ll_temac_bd_init(dev); - } - - memcpy(tx_buffer, (void *)buffer, length); - flush_cache((u32)tx_buffer, length); - - tx_bd.stat = BDSTAT_SOP_MASK | BDSTAT_EOP_MASK | - BDSTAT_STOP_ON_END_MASK; - tx_bd.buf_len = length; - flush_cache((u32)&tx_bd, sizeof(tx_bd)); - - sdma_out_be32(priv, TX_CURDESC_PTR, (u32)&tx_bd); - sdma_out_be32(priv, TX_TAILDESC_PTR, (u32)&tx_bd); /* DMA start */ - - do { - flush_cache((u32)&tx_bd, sizeof(tx_bd)); - } while (!(tx_bd.stat & BDSTAT_COMPLETED_MASK)); - - return 0; -} - -static int ll_temac_recv_sdma(struct eth_device *dev) -{ - int length; - struct ll_priv *priv = dev->priv; - - if (xps_ll_temac_dma_error(dev)) { - xps_ll_temac_reset_dma(dev); - xps_ll_temac_bd_init(dev); - } - - flush_cache((u32)&rx_bd, sizeof(rx_bd)); - - if (!(rx_bd.stat & BDSTAT_COMPLETED_MASK)) + if (!ll_temac_indirect_get(regs, TEMAC_EMMC, &emmc_reg)) return 0; - /* - * Read out the packet info and start the DMA - * onto the second buffer to enable the ethernet rx - * path to run in parallel with sw processing - * packets. - */ - length = rx_bd.app5 & 0x3FFF; /* max length mask */ - if (length > 0) - NetReceive(rx_bd.phys_buf_p, length); - - /* flip the buffer and re-enable the DMA. */ - flush_cache((u32)rx_bd.phys_buf_p, length); - - rx_bd.buf_len = PKTSIZE_ALIGN; - rx_bd.stat = 0; - rx_bd.app5 = 0; - - flush_cache((u32)&rx_bd, sizeof(rx_bd)); - sdma_out_be32(priv, RX_TAILDESC_PTR, (u32)&rx_bd); - - return length; -} - -#ifdef DEBUG -static void debugll(struct eth_device *dev, int count) -{ - struct ll_priv *priv = dev->priv; - struct ll_fifo_s *ll_fifo = (void *)priv->ctrl; - - printf("%d fifo isr 0x%08x, fifo_ier 0x%08x, fifo_rdfr 0x%08x, " - "fifo_rdfo 0x%08x fifo_rlr 0x%08x\n", count, - in_be32(&ll_fifo->isr), in_be32(&ll_fifo->ier), - in_be32(&ll_fifo->rdfr), in_be32(&ll_fifo->rdfo), - in_be32(&ll_fifo->rlf)); -} -#endif - -static int ll_temac_send_fifo(struct eth_device *dev, - void *buffer, int length) -{ - struct ll_priv *priv = dev->priv; - struct ll_fifo_s *ll_fifo = (void *)priv->ctrl; - u32 *buf = (u32 *)buffer; - u32 i; - - for (i = 0; i < length; i += 4) - out_be32(&ll_fifo->tdfd, *buf++); + emmc_reg &= ~EMMC_LSPD_MASK; + emmc_reg |= speed; - out_be32(&ll_fifo->tlf, length); - return 0; -} - -static int ll_temac_recv_fifo(struct eth_device *dev) -{ - struct ll_priv *priv = dev->priv; - struct ll_fifo_s *ll_fifo = (void *)priv->ctrl; - u32 i, len = 0; - u32 *buf = (u32 *)&rx_buffer; - - if (in_be32(&ll_fifo->isr) & LL_FIFO_ISR_RC_COMPLETE) { - out_be32(&ll_fifo->isr, 0xffffffff); /* reset isr */ - - len = in_be32(&ll_fifo->rlf) & 0x7FF; + if (!ll_temac_indirect_set(regs, TEMAC_EMMC, emmc_reg)) + return 0; - for (i = 0; i < len; i += 4) - *buf++ = in_be32(&ll_fifo->rdfd); + printf("%s: PHY is %s with %dbase%s, %s%s\n", + dev->name, phydev->drv->name, + phydev->speed, (phydev->port == PORT_TP) ? "T" : "X", + (phydev->duplex) ? "FDX" : "HDX", + (phydev->port == PORT_OTHER) ? ", unkown mode" : ""); -#ifdef DEBUG - debugll(dev, 1); -#endif - NetReceive((uchar *)&rx_buffer, len); - } - return len; + return 1; } /* setup mac addr */ -static int ll_temac_addr_setup(struct eth_device *dev) +static int ll_temac_setup_mac_addr(struct eth_device *dev) { - int val; + struct temac_reg *regs = (struct temac_reg *)dev->iobase; + u32 val; /* set up unicast MAC address filter */ val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | - (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); - xps_ll_temac_indirect_set(dev, 0, UAW0, val); - val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; - xps_ll_temac_indirect_set(dev, 0, UAW1, val); + (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); + val &= UAW0_UADDR_MASK; - return 0; -} - -static int xps_ll_temac_init(struct eth_device *dev, bd_t *bis) -{ - struct ll_priv *priv = dev->priv; - struct ll_fifo_s *ll_fifo = (void *)priv->ctrl; + if (!ll_temac_indirect_set(regs, TEMAC_UAW0, val)) + return 1; - if (priv->mode & SDMA_BIT) { - xps_ll_temac_reset_dma(dev); - xps_ll_temac_bd_init(dev); - } else { - out_be32(&ll_fifo->tdfr, 0x000000a5); /* Fifo reset key */ - out_be32(&ll_fifo->rdfr, 0x000000a5); /* Fifo reset key */ - out_be32(&ll_fifo->isr, 0xFFFFFFFF); /* Reset status register */ - out_be32(&ll_fifo->ier, 0); /* Disable all IRQs */ - } + val = ((dev->enetaddr[5] << 8) | dev->enetaddr[4]); + val &= UAW1_UADDR_MASK; - xps_ll_temac_indirect_set(dev, 0, MC, - MDIO_ENABLE_MASK | MDIO_CLOCK_DIV_100MHz); + if (!ll_temac_indirect_set(regs, TEMAC_UAW1, val)) + return 1; - /* Promiscuous mode disable */ - xps_ll_temac_indirect_set(dev, 0, AFM, 0); - /* Enable Receiver - RX bit */ - xps_ll_temac_indirect_set(dev, 0, RCW1, 0x10000000); - /* Enable Transmitter - TX bit */ - xps_ll_temac_indirect_set(dev, 0, TC, 0x10000000); return 0; } /* halt device */ static void ll_temac_halt(struct eth_device *dev) { -#ifdef ETH_HALTING - struct ll_priv *priv = dev->priv; + struct ll_temac *ll_temac = dev->priv; + struct temac_reg *regs = (struct temac_reg *)dev->iobase; /* Disable Receiver */ - xps_ll_temac_indirect_set(dev, 0, RCW1, 0); + ll_temac_indirect_set(regs, TEMAC_RCW0, 0); + /* Disable Transmitter */ - xps_ll_temac_indirect_set(dev, 0, TC, 0); + ll_temac_indirect_set(regs, TEMAC_TC, 0); - if (priv->mode & SDMA_BIT) { - sdma_out_be32(priv->ctrl, DMA_CONTROL_REG, DMA_CONTROL_RESET); - while (sdma_in_be32(priv->ctrl, DMA_CONTROL_REG) - & DMA_CONTROL_RESET) - ; - } -#endif + if (ll_temac->ctrlhalt) + ll_temac->ctrlhalt(dev); + + /* Shut down the PHY, as needed */ + phy_shutdown(ll_temac->phydev); } static int ll_temac_init(struct eth_device *dev, bd_t *bis) { -#if DEBUG - int i; -#endif - xps_ll_temac_init(dev, bis); + struct ll_temac *ll_temac = dev->priv; + int ret; printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08lx.\n", dev->name, dev->index, dev->iobase); @@ -663,98 +237,166 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis) if (!ll_temac_setup_ctrl(dev)) return -1; -#if DEBUG - for (i = 0; i < 32; i++) - read_phy_reg(dev, i); -#endif + /* Start up the PHY */ + ret = phy_startup(ll_temac->phydev); + if (ret) { + printf("%s: Could not initialize PHY %s\n", + dev->name, ll_temac->phydev->dev->name); + return ret; + } - if (!xps_ll_temac_phy_ctrl(dev)) { + if (!ll_temac_adjust_link(dev)) { ll_temac_halt(dev); return -1; } - return 0; + /* If there's no link, fail */ + return ll_temac->phydev->link ? 0 : -1; } -static int ll_temac_miiphy_read(const char *devname, uchar addr, - uchar reg, ushort *val) +/* + * Discover which PHY is attached to the device, and configure it + * properly. If the PHY is not recognized, then return 0 + * (failure). Otherwise, return 1 + */ +static int ll_temac_phy_init(struct eth_device *dev) { - struct eth_device *dev = eth_get_dev(); + struct ll_temac *ll_temac = dev->priv; + struct phy_device *phydev; + unsigned int supported = PHY_GBIT_FEATURES; - *val = xps_ll_temac_hostif_get(dev, 0, addr, reg); /* emac = 0 */ + /* interface - look at driver/net/tsec.c */ + phydev = phy_connect(ll_temac->bus, ll_temac->phyaddr, + dev, PHY_INTERFACE_MODE_NONE); - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); - return 0; -} - -static int ll_temac_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) -{ - struct eth_device *dev = eth_get_dev(); - - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); + phydev->supported &= supported; + phydev->advertising = phydev->supported; - xps_ll_temac_hostif_set(dev, 0, addr, reg, val); + ll_temac->phydev = phydev; - return 0; -} + phy_config(phydev); -static int ll_temac_bus_reset(struct mii_dev *bus) -{ - debug("Just bus reset\n"); - return 0; + return 1; } -/* mode bits: 0bit - fifo(0)/sdma(1):SDMA_BIT, 1bit - no dcr(0)/dcr(1):DCR_BIT - * ctrl - control address for file/sdma */ -int xilinx_ll_temac_initialize(bd_t *bis, unsigned long base_addr, - int mode, unsigned long ctrl) +/* + * Initialize a single ll_temac devices + * + * Returns the result of ll_temac phy interface that were initialized + */ +int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf) { struct eth_device *dev; - struct ll_priv *priv; + struct ll_temac *ll_temac; dev = calloc(1, sizeof(*dev)); if (dev == NULL) - return -1; + return 0; - dev->priv = calloc(1, sizeof(struct ll_priv)); - if (dev->priv == NULL) { + ll_temac = calloc(1, sizeof(struct ll_temac)); + if (ll_temac == NULL) { free(dev); - return -1; + return 0; } - priv = dev->priv; - - sprintf(dev->name, "Xlltem.%lx", base_addr); - - dev->iobase = base_addr; - priv->ctrl = ctrl; - priv->mode = mode; + /* use given name or generate its own unique name */ + if (devinf->devname) { + strncpy(dev->name, devinf->devname, sizeof(dev->name)); + } else { + snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr); + devinf->devname = dev->name; + } -#ifdef CONFIG_PHY_ADDR - priv->phyaddr = CONFIG_PHY_ADDR; -#else - priv->phyaddr = -1; -#endif + dev->iobase = devinf->base_addr; + dev->priv = ll_temac; dev->init = ll_temac_init; dev->halt = ll_temac_halt; - dev->write_hwaddr = ll_temac_addr_setup; - - if (priv->mode & SDMA_BIT) { - dev->send = ll_temac_send_sdma; + dev->write_hwaddr = ll_temac_setup_mac_addr; + + ll_temac->ctrladdr = devinf->ctrl_addr; + if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_PLB) { +#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) + if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_DCR) { + ll_temac_collect_xldcr_sdma_reg_addr(dev); + ll_temac->in32 = ll_temac_xldcr_in32; + ll_temac->out32 = ll_temac_xldcr_out32; + } else +#endif + { + ll_temac_collect_xlplb_sdma_reg_addr(dev); + ll_temac->in32 = ll_temac_xlplb_in32; + ll_temac->out32 = ll_temac_xlplb_out32; + } + ll_temac->ctrlinit = ll_temac_init_sdma; + ll_temac->ctrlhalt = ll_temac_halt_sdma; + ll_temac->ctrlreset = ll_temac_reset_sdma; dev->recv = ll_temac_recv_sdma; + dev->send = ll_temac_send_sdma; } else { - dev->send = ll_temac_send_fifo; + ll_temac->in32 = NULL; + ll_temac->out32 = NULL; + ll_temac->ctrlinit = NULL; + ll_temac->ctrlhalt = NULL; + ll_temac->ctrlreset = ll_temac_reset_fifo; dev->recv = ll_temac_recv_fifo; + dev->send = ll_temac_send_fifo; } + /* Link to specified MDIO bus */ + strncpy(ll_temac->mdio_busname, devinf->mdio_busname, MDIO_NAME_LEN); + ll_temac->bus = miiphy_get_dev_by_name(ll_temac->mdio_busname); + + /* Looking for a valid PHY address if it is not yet set */ + if (devinf->phyaddr == -1) + ll_temac->phyaddr = ll_temac_phy_addr(ll_temac->bus); + else + ll_temac->phyaddr = devinf->phyaddr; + eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_register(dev->name, ll_temac_miiphy_read, ll_temac_miiphy_write); - priv->bus = miiphy_get_dev_by_name(dev->name); - priv->bus->reset = ll_temac_bus_reset; -#endif - return 1; + /* Try to initialize PHY here, and return */ + return ll_temac_phy_init(dev); +} + +/* + * Initialize a single ll_temac device with its mdio bus behind ll_temac + * + * Returns 1 if the ll_temac device and the mdio bus were initialized + * otherwise returns 0 + */ +int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, + unsigned long ctrl_addr) +{ + struct ll_temac_info devinf; + struct ll_temac_mdio_info mdioinf; + int ret; + + /* prepare the internal driver informations */ + devinf.flags = flags; + devinf.base_addr = base_addr; + devinf.ctrl_addr = ctrl_addr; + devinf.devname = NULL; + devinf.phyaddr = -1; + + mdioinf.name = devinf.mdio_busname = NULL; + mdioinf.regs = (struct temac_reg *)devinf.base_addr; + + ret = xilinx_ll_temac_mdio_initialize(bis, &mdioinf); + if (ret >= 0) { + + /* + * If there was no MDIO bus name then take over the + * new automaticaly generated by the MDIO init code. + */ + if (mdioinf.name != devinf.mdio_busname) + devinf.mdio_busname = mdioinf.name; + + ret = xilinx_ll_temac_initialize(bis, &devinf); + if (ret > 0) + return 1; + + } + + return 0; } diff --git a/drivers/net/xilinx_ll_temac.h b/drivers/net/xilinx_ll_temac.h new file mode 100644 index 00000000000..56362ba2077 --- /dev/null +++ b/drivers/net/xilinx_ll_temac.h @@ -0,0 +1,307 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * LL_TEMAC interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_ +#define _XILINX_LL_TEMAC_ + +#include +#include +#include +#include + +#include +#include + +#include "xilinx_ll_temac_sdma.h" + +#if !defined(__BIG_ENDIAN) +# error LL_TEMAC requires big endianess +#endif + +/* + * TEMAC Memory and Register Definition + * + * [1]: [0]/ip_documentation/xps_ll_temac.pdf + * page 19, Memory and Register Descriptions + */ +struct temac_reg { + /* direct soft registers (low part) */ + u32 raf; /* Reset and Address Filter */ + u32 tpf; /* Transmit Pause Frame */ + u32 ifgp; /* Transmit Inter Frame Gap Adjustment */ + u32 is; /* Interrupt Status */ + u32 ip; /* Interrupt Pending */ + u32 ie; /* Interrupt Enable */ + u32 ttag; /* Transmit VLAN Tag */ + u32 rtag; /* Receive VLAN Tag */ + /* hard TEMAC registers */ + u32 msw; /* Most Significant Word Data */ + u32 lsw; /* Least Significant Word Data */ + u32 ctl; /* Control */ + u32 rdy; /* Ready Status */ + /* direct soft registers (high part) */ + u32 uawl; /* Unicast Address Word Lower */ + u32 uawu; /* Unicast Address Word Upper */ + u32 tpid0; /* VLAN TPID Word 0 */ + u32 tpid1; /* VLAN TPID Word 1 */ +}; + +/* Reset and Address Filter Registers (raf), [1] p25 */ +#define RAF_SR (1 << 13) +#define RAF_EMFE (1 << 12) +#define RAF_NFE (1 << 11) +#define RAF_RVSTM_POS 9 +#define RAF_RVSTM_MASK (3 << RAF_RVSTM_POS) +#define RAF_TVSTM_POS 7 +#define RAF_TVSTM_MASK (3 << RAF_TVSTM_POS) +#define RAF_RVTM_POS 5 +#define RAF_RVTM_MASK (3 << RAF_RVTM_POS) +#define RAF_TVTM_POS 3 +#define RAF_TVTM_MASK (3 << RAF_TVTM_POS) +#define RAF_BCREJ (1 << 2) +#define RAF_MCREJ (1 << 1) +#define RAF_HTRST (1 << 0) + +/* Transmit Pause Frame Registers (tpf), [1] p28 */ +#define TPF_TPFV_POS 0 +#define TPF_TPFV_MASK (0xFFFF << TPF_TPFV_POS) + +/* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */ +#define IFGP_POS 0 +#define IFGP_MASK (0xFF << IFGP_POS) + +/* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */ +#define ISPE_MR (1 << 7) +#define ISPE_RDL (1 << 6) +#define ISPE_TC (1 << 5) +#define ISPE_RFO (1 << 4) +#define ISPE_RR (1 << 3) +#define ISPE_RC (1 << 2) +#define ISPE_AN (1 << 1) +#define ISPE_HAC (1 << 0) + +/* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */ +#define TRTAG_TPID_POS 16 +#define TRTAG_TPID_MASK (0xFFFF << TRTAG_TPID_POS) +#define TRTAG_PRIO_POS 13 +#define TRTAG_PRIO_MASK (7 << TRTAG_PRIO_POS) +#define TRTAG_CFI (1 << 12) +#define TRTAG_VID_POS 0 +#define TRTAG_VID_MASK (0xFFF << TRTAG_VID_POS) + +/* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */ +#define MLSW_POS 0 +#define MLSW_MASK (~0UL << MLSW_POS) + +/* LSW Data Register for PHY addresses (lsw), [1] p66 */ +#define LSW_REGAD_POS 0 +#define LSW_REGAD_MASK (0x1F << LSW_REGAD_POS) +#define LSW_PHYAD_POS 5 +#define LSW_PHYAD_MASK (0x1F << LSW_PHYAD_POS) + +/* LSW Data Register for PHY data (lsw), [1] p66 */ +#define LSW_REGDAT_POS 0 +#define LSW_REGDAT_MASK (0xFFFF << LSW_REGDAT_POS) + +/* Control Register (ctl), [1] p47 */ +#define CTL_WEN (1 << 15) +#define CTL_ADDR_POS 0 +#define CTL_ADDR_MASK (0x3FF << CTL_ADDR_POS) + +/* Ready Status Register Ethernet (rdy), [1] p48 */ +#define RSE_HACS_RDY (1 << 14) +#define RSE_CFG_WR (1 << 6) +#define RSE_CFG_RR (1 << 5) +#define RSE_AF_WR (1 << 4) +#define RSE_AF_RR (1 << 3) +#define RSE_MIIM_WR (1 << 2) +#define RSE_MIIM_RR (1 << 1) +#define RSE_FABR_RR (1 << 0) + +/* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */ +#define UAWL_UADDR_POS 0 +#define UAWL_UADDR_MASK (~0UL << UAWL_UADDR_POS) +#define UAWU_UADDR_POS 0 +#define UAWU_UADDR_MASK (0xFFFF << UAWU_UADDR_POS) + +/* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */ +#define TPID0_V0_POS 0 +#define TPID0_V0_MASK (0xFFFF << TPID0_V0_POS) +#define TPID0_V1_POS 16 +#define TPID0_V1_MASK (0xFFFF << TPID0_V1_POS) +#define TPID1_V2_POS 0 +#define TPID1_V2_MASK (0xFFFF << TPID1_V2_POS) +#define TPID1_V3_POS 16 +#define TPID1_V3_MASK (0xFFFF << TPID1_V3_POS) + +/* + * TEMAC Indirectly Addressable Register Index Enumeration + * + * [0]: http://www.xilinx.com/support/documentation + * + * [1]: [0]/ip_documentation/xps_ll_temac.pdf + * page 23, PLB Indirectly Addressable TEMAC Registers + */ +enum temac_ctrl { + TEMAC_RCW0 = 0x200, + TEMAC_RCW1 = 0x240, + TEMAC_TC = 0x280, + TEMAC_FCC = 0x2C0, + TEMAC_EMMC = 0x300, + TEMAC_PHYC = 0x320, + TEMAC_MC = 0x340, + TEMAC_UAW0 = 0x380, + TEMAC_UAW1 = 0x384, + TEMAC_MAW0 = 0x388, + TEMAC_MAW1 = 0x38C, + TEMAC_AFM = 0x390, + TEMAC_TIS = 0x3A0, + TEMAC_TIE = 0x3A4, + TEMAC_MIIMWD = 0x3B0, + TEMAC_MIIMAI = 0x3B4 +}; + +/* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */ +#define RCW0_PADDR_POS 0 +#define RCW0_PADDR_MASK (~0UL << RCW_PADDR_POS) +#define RCW1_RST (1 << 31) +#define RCW1_JUM (1 << 30) +#define RCW1_FCS (1 << 29) +#define RCW1_RX (1 << 28) +#define RCW1_VLAN (1 << 27) +#define RCW1_HD (1 << 26) +#define RCW1_LT_DIS (1 << 25) +#define RCW1_PADDR_POS 0 +#define RCW1_PADDR_MASK (0xFFFF << RCW_PADDR_POS) + +/* Transmit Configuration Registers (TC), [1] p52 */ +#define TC_RST (1 << 31) +#define TC_JUM (1 << 30) +#define TC_FCS (1 << 29) +#define TC_TX (1 << 28) +#define TC_VLAN (1 << 27) +#define TC_HD (1 << 26) +#define TC_IFG (1 << 25) + +/* Flow Control Configuration Registers (FCC), [1] p54 */ +#define FCC_FCTX (1 << 30) +#define FCC_FCRX (1 << 29) + +/* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */ +#define EMMC_LSPD_POS 30 +#define EMMC_LSPD_MASK (3 << EMMC_LSPD_POS) +#define EMMC_LSPD_1000 (2 << EMMC_LSPD_POS) +#define EMMC_LSPD_100 (1 << EMMC_LSPD_POS) +#define EMMC_LSPD_10 0 +#define EMMC_RGMII (1 << 29) +#define EMMC_SGMII (1 << 28) +#define EMMC_GPCS (1 << 27) +#define EMMC_HOST (1 << 26) +#define EMMC_TX16 (1 << 25) +#define EMMC_RX16 (1 << 24) + +/* RGMII/SGMII Configuration Registers (PHYC), [1] p56 */ +#define PHYC_SLSPD_POS 30 +#define PHYC_SLSPD_MASK (3 << EMMC_SLSPD_POS) +#define PHYC_SLSPD_1000 (2 << EMMC_SLSPD_POS) +#define PHYC_SLSPD_100 (1 << EMMC_SLSPD_POS) +#define PHYC_SLSPD_10 0 +#define PHYC_RLSPD_POS 2 +#define PHYC_RLSPD_MASK (3 << EMMC_RLSPD_POS) +#define PHYC_RLSPD_1000 (2 << EMMC_RLSPD_POS) +#define PHYC_RLSPD_100 (1 << EMMC_RLSPD_POS) +#define PHYC_RLSPD_10 0 +#define PHYC_RGMII_HD (1 << 1) +#define PHYC_RGMII_LINK (1 << 0) + +/* Management Configuration Registers (MC), [1] p57 */ +#define MC_MDIOEN (1 << 6) +#define MC_CLKDIV_POS 0 +#define MC_CLKDIV_MASK (0x3F << MC_CLKDIV_POS) + +/* + * fHOSTCLK fMDC = fHOSTCLK + * fMDC = ------------------- ---------> MC_CLKDIV = -------- - 1 + * (1 + MC_CLKDIV) * 2 2.5 MHz 5MHz + */ +#define MC_CLKDIV(f, m) ((f / (2 * m)) - 1) +#define MC_CLKDIV_25(f) MC_CLKDIV(f, 2500000) +#define MC_CLKDIV_20(f) MC_CLKDIV(f, 2000000) +#define MC_CLKDIV_15(f) MC_CLKDIV(f, 1500000) +#define MC_CLKDIV_10(f) MC_CLKDIV(f, 1000000) + +/* Unicast Address Word 0, 1 Registers (UAW0, UAW1), [1] p58-59 */ +#define UAW0_UADDR_POS 0 +#define UAW0_UADDR_MASK (~0UL << UAW0_UADDR_POS) +#define UAW1_UADDR_POS 0 +#define UAW1_UADDR_MASK (0xFFFF << UAW1_UADDR_POS) + +/* Multicast Address Word 0, 1 Registers (MAW0, MAW1), [1] p60 */ +#define MAW0_MADDR_POS 0 +#define MAW0_MADDR_MASK (~0UL << MAW0_MADDR_POS) +#define MAW1_RNW (1 << 23) +#define MAW1_MAIDX_POS 16 +#define MAW1_MAIDX_MASK (3 << MAW1_MAIDX_POS) +#define MAW1_MADDR_POS 0 +#define MAW1_MADDR_MASK (0xFFFF << MAW1_MADDR_POS) + +/* Address Filter Mode Registers (AFM), [1] p63 */ +#define AFM_PM (1 << 31) + +/* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */ +#define TISE_CFG_W (1 << 6) +#define TISE_CFG_R (1 << 5) +#define TISE_AF_W (1 << 4) +#define TISE_AF_R (1 << 3) +#define TISE_MIIM_W (1 << 2) +#define TISE_MIIM_R (1 << 1) +#define TISE_FABR_R (1 << 0) + +/* MII Management Write Data Registers (MIIMWD), [1] p66 */ +#define MIIMWD_DATA_POS 0 +#define MIIMWD_DATA_MASK (0xFFFF << MIIMWD_DATA_POS) + +/* Ethernet interface ready status */ +int ll_temac_check_status(struct temac_reg *regs, u32 mask); + +/* Indirect write to ll_temac. */ +int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data); + +/* Indirect read from ll_temac. */ +int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data); + +struct ll_temac { + phys_addr_t ctrladdr; + phys_addr_t sdma_reg_addr[SDMA_CTRL_REGNUMS]; + + unsigned (*in32)(phys_addr_t); + void (*out32)(phys_addr_t, unsigned); + + int (*ctrlinit) (struct eth_device *); + int (*ctrlhalt) (struct eth_device *); + int (*ctrlreset) (struct eth_device *); + + int phyaddr; + struct phy_device *phydev; + struct mii_dev *bus; + char mdio_busname[MDIO_NAME_LEN]; +}; + +#endif /* _XILINX_LL_TEMAC_ */ diff --git a/drivers/net/xilinx_ll_temac_fifo.c b/drivers/net/xilinx_ll_temac_fifo.c new file mode 100644 index 00000000000..78319d7d918 --- /dev/null +++ b/drivers/net/xilinx_ll_temac_fifo.c @@ -0,0 +1,139 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * FIFO sub-controller + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * CREDITS: tsec driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [F]: [0]/ip_documentation/xps_ll_fifo.pdf + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ + +#include +#include +#include + +#include +#include + +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_fifo.h" + +int ll_temac_reset_fifo(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr; + + out_be32(&fifo_ctrl->tdfr, LL_FIFO_TDFR_KEY); + out_be32(&fifo_ctrl->rdfr, LL_FIFO_RDFR_KEY); + out_be32(&fifo_ctrl->isr, ~0UL); + out_be32(&fifo_ctrl->ier, 0); + + return 0; +} + +int ll_temac_recv_fifo(struct eth_device *dev) +{ + int i, length = 0; + u32 *buf = (u32 *)net_rx_packets[0]; + struct ll_temac *ll_temac = dev->priv; + struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr; + + if (in_be32(&fifo_ctrl->isr) & LL_FIFO_ISR_RC) { + + /* reset isr */ + out_be32(&fifo_ctrl->isr, ~0UL); + + /* + * MAYBE here: + * while (fifo_ctrl->isr); + */ + + /* + * The length is written (into RLR) by the XPS LL FIFO + * when the packet is received across the RX LocalLink + * interface and the receive data FIFO had enough + * locations that all of the packet data has been saved. + * The RLR should only be read when a receive packet is + * available for processing (the receive occupancy is + * not zero). Once the RLR is read, the receive packet + * data should be read from the receive data FIFO before + * the RLR is read again. + * + * [F] page 17, Receive Length Register (RLR) + */ + if (in_be32(&fifo_ctrl->rdfo) & LL_FIFO_RDFO_MASK) { + length = in_be32(&fifo_ctrl->rlf) & LL_FIFO_RLF_MASK; + } else { + printf("%s: Got error, no receive occupancy\n", + __func__); + return -1; + } + + if (length > PKTSIZE_ALIGN) { + printf("%s: Got error, receive package too big (%i)\n", + __func__, length); + ll_temac_reset_fifo(dev); + return -1; + } + + for (i = 0; i < length; i += 4) + *buf++ = in_be32(&fifo_ctrl->rdfd); + + net_process_received_packet(net_rx_packets[0], length); + } + + return 0; +} + +int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length) +{ + int i; + u32 *buf = (u32 *)packet; + struct ll_temac *ll_temac = dev->priv; + struct fifo_ctrl *fifo_ctrl = (void *)ll_temac->ctrladdr; + + if (length < LL_FIFO_TLF_MIN) { + printf("%s: Got error, transmit package too small (%i)\n", + __func__, length); + return -1; + } + + if (length > LL_FIFO_TLF_MAX) { + printf("%s: Got error, transmit package too big (%i)\n", + __func__, length); + return -1; + } + + for (i = 0; i < length; i += 4) + out_be32(&fifo_ctrl->tdfd, *buf++); + + /* + * Once the packet length is written to the TLR it is + * automatically moved to the transmit data FIFO with + * the packet data freeing up the TLR for another value. + * The packet length must be written to the TLR after + * the packet data is written to the transmit data FIFO. + * It is not valid to write data for multiple packets + * to the transmit data FIFO before writing the packet + * length values. + * + * [F] page 17, Transmit Length Register (TLR) + */ + out_be32(&fifo_ctrl->tlf, length); + + return 0; +} diff --git a/drivers/net/xilinx_ll_temac_fifo.h b/drivers/net/xilinx_ll_temac_fifo.h new file mode 100644 index 00000000000..c1bf7cc641b --- /dev/null +++ b/drivers/net/xilinx_ll_temac_fifo.h @@ -0,0 +1,118 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * FIFO sub-controller interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_FIFO_ +#define _XILINX_LL_TEMAC_FIFO_ + +#include + +#include +#include + +#if !defined(__BIG_ENDIAN) +# error LL_TEMAC requires big endianess +#endif + +/* + * FIFO Register Definition + * + * Used for memory mapped access from and to (Rd/Td) the LocalLink (LL) + * Tri-Mode Ether MAC (TEMAC) via the 2 kb full duplex FIFO Controller, + * one for each. + * + * [1]: [0]/ip_documentation/xps_ll_fifo.pdf + * page 10, Registers Definition + */ +struct fifo_ctrl { + u32 isr; /* Interrupt Status Register (RW) */ + u32 ier; /* Interrupt Enable Register (RW) */ + u32 tdfr; /* Transmit Data FIFO Reset (WO) */ + u32 tdfv; /* Transmit Data FIFO Vacancy (RO) */ + u32 tdfd; /* Transmit Data FIFO 32bit wide Data write port (WO) */ + u32 tlf; /* Transmit Length FIFO (WO) */ + u32 rdfr; /* Receive Data FIFO Reset (WO) */ + u32 rdfo; /* Receive Data FIFO Occupancy (RO) */ + u32 rdfd; /* Receive Data FIFO 32bit wide Data read port (RO) */ + u32 rlf; /* Receive Length FIFO (RO) */ + u32 llr; /* LocalLink Reset (WO) */ +}; + +/* Interrupt Status Register (ISR), [1] p11 */ +#define LL_FIFO_ISR_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ +#define LL_FIFO_ISR_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ +#define LL_FIFO_ISR_RPUE (1 << 29) /* Receive Packet Underrun Error */ +#define LL_FIFO_ISR_TPOE (1 << 28) /* Transmit Packet Overrun Error */ +#define LL_FIFO_ISR_TC (1 << 27) /* Transmit Complete */ +#define LL_FIFO_ISR_RC (1 << 26) /* Receive Complete */ +#define LL_FIFO_ISR_TSE (1 << 25) /* Transmit Size Error */ +#define LL_FIFO_ISR_TRC (1 << 24) /* Transmit Reset Complete */ +#define LL_FIFO_ISR_RRC (1 << 23) /* Receive Reset Complete */ + +/* Interrupt Enable Register (IER), [1] p12/p13 */ +#define LL_FIFO_IER_RPURE (1 << 31) /* Receive Packet Underrun Read Err */ +#define LL_FIFO_IER_RPORE (1 << 30) /* Receive Packet Overrun Read Err */ +#define LL_FIFO_IER_RPUE (1 << 29) /* Receive Packet Underrun Error */ +#define LL_FIFO_IER_TPOE (1 << 28) /* Transmit Packet Overrun Error */ +#define LL_FIFO_IER_TC (1 << 27) /* Transmit Complete */ +#define LL_FIFO_IER_RC (1 << 26) /* Receive Complete */ +#define LL_FIFO_IER_TSE (1 << 25) /* Transmit Size Error */ +#define LL_FIFO_IER_TRC (1 << 24) /* Transmit Reset Complete */ +#define LL_FIFO_IER_RRC (1 << 23) /* Receive Reset Complete */ + +/* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */ +#define LL_FIFO_TDFR_KEY 0x000000A5UL + +/* Transmit Data FIFO Vacancy (TDFV), [1] p14 */ +#define LL_FIFO_TDFV_POS 0 +#define LL_FIFO_TDFV_MASK (0x000001FFUL << LL_FIFO_TDFV_POS) + +/* Transmit Length FIFO (TLF), [1] p16/p17 */ +#define LL_FIFO_TLF_POS 0 +#define LL_FIFO_TLF_MASK (0x000007FFUL << LL_FIFO_TLF_POS) +#define LL_FIFO_TLF_MIN ((4 * sizeof(u32)) & LL_FIFO_TLF_MASK) +#define LL_FIFO_TLF_MAX ((510 * sizeof(u32)) & LL_FIFO_TLF_MASK) + +/* Receive Data FIFO Reset (RDFR), [1] p15 */ +#define LL_FIFO_RDFR_KEY 0x000000A5UL + +/* Receive Data FIFO Occupancy (RDFO), [1] p16 */ +#define LL_FIFO_RDFO_POS 0 +#define LL_FIFO_RDFO_MASK (0x000001FFUL << LL_FIFO_RDFO_POS) + +/* Receive Length FIFO (RLF), [1] p17/p18 */ +#define LL_FIFO_RLF_POS 0 +#define LL_FIFO_RLF_MASK (0x000007FFUL << LL_FIFO_RLF_POS) +#define LL_FIFO_RLF_MIN ((4 * sizeof(uint32)) & LL_FIFO_RLF_MASK) +#define LL_FIFO_RLF_MAX ((510 * sizeof(uint32)) & LL_FIFO_RLF_MASK) + +/* LocalLink Reset (LLR), [1] p18 */ +#define LL_FIFO_LLR_KEY 0x000000A5UL + + +/* reset FIFO and IRQ, disable interrupts */ +int ll_temac_reset_fifo(struct eth_device *dev); + +/* receive buffered data from FIFO (polling ISR) */ +int ll_temac_recv_fifo(struct eth_device *dev); + +/* send buffered data to FIFO */ +int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length); + +#endif /* _XILINX_LL_TEMAC_FIFO_ */ diff --git a/drivers/net/xilinx_ll_temac_mdio.c b/drivers/net/xilinx_ll_temac_mdio.c new file mode 100644 index 00000000000..b7bab794e57 --- /dev/null +++ b/drivers/net/xilinx_ll_temac_mdio.c @@ -0,0 +1,177 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * MDIO bus access + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * CREDITS: tsec driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ + +#include +#include +#include +#include +#include +#include + +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_mdio.h" + +#if !defined(CONFIG_MII) +# error "LL_TEMAC requires MII -- missing CONFIG_MII" +#endif + +#if !defined(CONFIG_PHYLIB) +# error "LL_TEMAC requires PHYLIB -- missing CONFIG_PHYLIB" +#endif + +/* + * Prior to PHY access, the MDIO clock must be setup. This driver will set a + * safe default that should work with PLB bus speeds of up to 150 MHz and keep + * the MDIO clock below 2.5 MHz. If the user wishes faster access to the PHY + * then the clock divisor can be set to a different value by setting the + * correct bus speed value with CONFIG_XILINX_LL_TEMAC_CLK. + */ +#if !defined(CONFIG_XILINX_LL_TEMAC_CLK) +#define MDIO_CLOCK_DIV MC_CLKDIV_10(150000000) +#else +#define MDIO_CLOCK_DIV MC_CLKDIV_25(CONFIG_XILINX_LL_TEMAC_CLK) +#endif + +static int ll_temac_mdio_setup(struct mii_dev *bus) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + + /* setup MDIO clock */ + ll_temac_indirect_set(regs, TEMAC_MC, + MC_MDIOEN | (MDIO_CLOCK_DIV & MC_CLKDIV_MASK)); + + return 0; +} + +/* + * Indirect MII PHY read via ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 67, Using the MII Management to Access PHY Registers + */ +int ll_temac_local_mdio_read(struct temac_reg *regs, int addr, int devad, + int regnum) +{ + out_be32(®s->lsw, + ((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) | + (regnum & LSW_REGAD_MASK)); + out_be32(®s->ctl, TEMAC_MIIMAI); + + ll_temac_check_status(regs, RSE_MIIM_RR); + + return in_be32(®s->lsw) & LSW_REGDAT_MASK; +} + +/* + * Indirect MII PHY write via ll_temac. + * + * http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf + * page 67, Using the MII Management to Access PHY Registers + */ +void ll_temac_local_mdio_write(struct temac_reg *regs, int addr, int devad, + int regnum, u16 value) +{ + out_be32(®s->lsw, (value & LSW_REGDAT_MASK)); + out_be32(®s->ctl, CTL_WEN | TEMAC_MIIMWD); + + out_be32(®s->lsw, + ((addr << LSW_PHYAD_POS) & LSW_PHYAD_MASK) | + (regnum & LSW_REGAD_MASK)); + out_be32(®s->ctl, CTL_WEN | TEMAC_MIIMAI); + + ll_temac_check_status(regs, RSE_MIIM_WR); +} + +int ll_temac_phy_read(struct mii_dev *bus, int addr, int devad, int regnum) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + + return ll_temac_local_mdio_read(regs, addr, devad, regnum); +} + +int ll_temac_phy_write(struct mii_dev *bus, int addr, int devad, int regnum, + u16 value) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + + ll_temac_local_mdio_write(regs, addr, devad, regnum, value); + + return 0; +} + +/* + * Use MII register 1 (MII status register) to detect PHY + * + * A Mask used to verify certain PHY features (register content) + * in the PHY detection register: + * Auto-negotiation support, 10Mbps half/full duplex support + */ +#define PHY_DETECT_REG MII_BMSR +#define PHY_DETECT_MASK (BMSR_10FULL | BMSR_10HALF | BMSR_ANEGCAPABLE) + +/* Looking for a valid PHY address */ +int ll_temac_phy_addr(struct mii_dev *bus) +{ + struct temac_reg *regs = (struct temac_reg *)bus->priv; + unsigned short val; + unsigned int phy; + + for (phy = PHY_MAX_ADDR; phy >= 0; phy--) { + val = ll_temac_local_mdio_read(regs, phy, 0, PHY_DETECT_REG); + if ((val != 0xFFFF) && + ((val & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + return phy; + } + } + + return -1; +} + +int xilinx_ll_temac_mdio_initialize(bd_t *bis, struct ll_temac_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate LL_TEMAC MDIO bus: %s\n", + info->name); + return -1; + } + + bus->read = ll_temac_phy_read; + bus->write = ll_temac_phy_write; + bus->reset = NULL; + + /* use given name or generate its own unique name */ + if (info->name) { + strncpy(bus->name, info->name, MDIO_NAME_LEN); + } else { + snprintf(bus->name, MDIO_NAME_LEN, "lltemii.%p", info->regs); + info->name = bus->name; + } + + bus->priv = info->regs; + + ll_temac_mdio_setup(bus); + return mdio_register(bus); +} diff --git a/drivers/net/xilinx_ll_temac_mdio.h b/drivers/net/xilinx_ll_temac_mdio.h new file mode 100644 index 00000000000..0603c64457f --- /dev/null +++ b/drivers/net/xilinx_ll_temac_mdio.h @@ -0,0 +1,50 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * MDIO bus access interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_MDIO_ +#define _XILINX_LL_TEMAC_MDIO_ + +#include +#include + +#include +#include + +#include "xilinx_ll_temac.h" + +int ll_temac_local_mdio_read(struct temac_reg *regs, int addr, int devad, + int regnum); +void ll_temac_local_mdio_write(struct temac_reg *regs, int addr, int devad, + int regnum, u16 value); + +int ll_temac_phy_read(struct mii_dev *bus, int addr, int devad, int regnum); +int ll_temac_phy_write(struct mii_dev *bus, int addr, int devad, int regnum, + u16 value); + +int ll_temac_phy_addr(struct mii_dev *bus); + +struct ll_temac_mdio_info { + struct temac_reg *regs; + char *name; +}; + +int xilinx_ll_temac_mdio_initialize(bd_t *bis, struct ll_temac_mdio_info *info); + +#endif /* _XILINX_LL_TEMAC_MDIO_ */ diff --git a/drivers/net/xilinx_ll_temac_sdma.c b/drivers/net/xilinx_ll_temac_sdma.c new file mode 100644 index 00000000000..07c5f6bf10c --- /dev/null +++ b/drivers/net/xilinx_ll_temac_sdma.c @@ -0,0 +1,366 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * SDMA sub-controller + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * CREDITS: tsec driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [M]: [0]/ip_documentation/mpmc.pdf + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ + +#include +#include +#include + +#include +#include + +#include "xilinx_ll_temac.h" +#include "xilinx_ll_temac_sdma.h" + +#define TX_BUF_CNT 2 + +static unsigned int rx_idx; /* index of the current RX buffer */ +static unsigned int tx_idx; /* index of the current TX buffer */ + +struct rtx_cdmac_bd { + struct cdmac_bd rx[PKTBUFSRX]; + struct cdmac_bd tx[TX_BUF_CNT]; +}; + +/* + * DMA Buffer Descriptor alignment + * + * If the address contained in the Next Descriptor Pointer register is not + * 8-word aligned or reaches beyond the range of available memory, the SDMA + * halts processing and sets the CDMAC_BD_STCTRL_ERROR bit in the respective + * status register (tx_chnl_sts or rx_chnl_sts). + * + * [1]: [0]/ip_documentation/mpmc.pdf + * page 161, Next Descriptor Pointer + */ +static struct rtx_cdmac_bd cdmac_bd __aligned(32); + +#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) + +/* + * Indirect DCR access operations mi{ft}dcr_xilinx() espacialy + * for Xilinx PowerPC implementations on FPGA. + * + * FIXME: This part should go up to arch/powerpc -- but where? + */ +#include +#define XILINX_INDIRECT_DCR_ADDRESS_REG 0 +#define XILINX_INDIRECT_DCR_ACCESS_REG 1 +inline unsigned mifdcr_xilinx(const unsigned dcrn) +{ + mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn); + return mfdcr(XILINX_INDIRECT_DCR_ACCESS_REG); +} +inline void mitdcr_xilinx(const unsigned dcrn, int val) +{ + mtdcr(XILINX_INDIRECT_DCR_ADDRESS_REG, dcrn); + mtdcr(XILINX_INDIRECT_DCR_ACCESS_REG, val); +} + +/* Xilinx Device Control Register (DCR) in/out accessors */ +inline unsigned ll_temac_xldcr_in32(phys_addr_t addr) +{ + return mifdcr_xilinx((const unsigned)addr); +} +inline void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value) +{ + mitdcr_xilinx((const unsigned)addr, value); +} + +void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + phys_addr_t dmac_ctrl = ll_temac->ctrladdr; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + ra[TX_NXTDESC_PTR] = dmac_ctrl + TX_NXTDESC_PTR; + ra[TX_CURBUF_ADDR] = dmac_ctrl + TX_CURBUF_ADDR; + ra[TX_CURBUF_LENGTH] = dmac_ctrl + TX_CURBUF_LENGTH; + ra[TX_CURDESC_PTR] = dmac_ctrl + TX_CURDESC_PTR; + ra[TX_TAILDESC_PTR] = dmac_ctrl + TX_TAILDESC_PTR; + ra[TX_CHNL_CTRL] = dmac_ctrl + TX_CHNL_CTRL; + ra[TX_IRQ_REG] = dmac_ctrl + TX_IRQ_REG; + ra[TX_CHNL_STS] = dmac_ctrl + TX_CHNL_STS; + ra[RX_NXTDESC_PTR] = dmac_ctrl + RX_NXTDESC_PTR; + ra[RX_CURBUF_ADDR] = dmac_ctrl + RX_CURBUF_ADDR; + ra[RX_CURBUF_LENGTH] = dmac_ctrl + RX_CURBUF_LENGTH; + ra[RX_CURDESC_PTR] = dmac_ctrl + RX_CURDESC_PTR; + ra[RX_TAILDESC_PTR] = dmac_ctrl + RX_TAILDESC_PTR; + ra[RX_CHNL_CTRL] = dmac_ctrl + RX_CHNL_CTRL; + ra[RX_IRQ_REG] = dmac_ctrl + RX_IRQ_REG; + ra[RX_CHNL_STS] = dmac_ctrl + RX_CHNL_STS; + ra[DMA_CONTROL_REG] = dmac_ctrl + DMA_CONTROL_REG; +} + +#endif /* CONFIG_XILINX_440 || ONFIG_XILINX_405 */ + +/* Xilinx Processor Local Bus (PLB) in/out accessors */ +inline unsigned ll_temac_xlplb_in32(phys_addr_t addr) +{ + return in_be32((void *)addr); +} +inline void ll_temac_xlplb_out32(phys_addr_t addr, unsigned value) +{ + out_be32((void *)addr, value); +} + +/* collect all register addresses for Xilinx PLB in/out accessors */ +void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct sdma_ctrl *sdma_ctrl = (void *)ll_temac->ctrladdr; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + ra[TX_NXTDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_nxtdesc_ptr; + ra[TX_CURBUF_ADDR] = (phys_addr_t)&sdma_ctrl->tx_curbuf_addr; + ra[TX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->tx_curbuf_length; + ra[TX_CURDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_curdesc_ptr; + ra[TX_TAILDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_taildesc_ptr; + ra[TX_CHNL_CTRL] = (phys_addr_t)&sdma_ctrl->tx_chnl_ctrl; + ra[TX_IRQ_REG] = (phys_addr_t)&sdma_ctrl->tx_irq_reg; + ra[TX_CHNL_STS] = (phys_addr_t)&sdma_ctrl->tx_chnl_sts; + ra[RX_NXTDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_nxtdesc_ptr; + ra[RX_CURBUF_ADDR] = (phys_addr_t)&sdma_ctrl->rx_curbuf_addr; + ra[RX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->rx_curbuf_length; + ra[RX_CURDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_curdesc_ptr; + ra[RX_TAILDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_taildesc_ptr; + ra[RX_CHNL_CTRL] = (phys_addr_t)&sdma_ctrl->rx_chnl_ctrl; + ra[RX_IRQ_REG] = (phys_addr_t)&sdma_ctrl->rx_irq_reg; + ra[RX_CHNL_STS] = (phys_addr_t)&sdma_ctrl->rx_chnl_sts; + ra[DMA_CONTROL_REG] = (phys_addr_t)&sdma_ctrl->dma_control_reg; +} + +/* Check for TX and RX channel errors. */ +static inline int ll_temac_sdma_error(struct eth_device *dev) +{ + int err; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + err = ll_temac->in32(ra[TX_CHNL_STS]) & CHNL_STS_ERROR; + err |= ll_temac->in32(ra[RX_CHNL_STS]) & CHNL_STS_ERROR; + + return err; +} + +int ll_temac_init_sdma(struct eth_device *dev) +{ + struct ll_temac *ll_temac = dev->priv; + struct cdmac_bd *rx_dp; + struct cdmac_bd *tx_dp; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + int i; + + printf("%s: SDMA: %d Rx buffers, %d Tx buffers\n", + dev->name, PKTBUFSRX, TX_BUF_CNT); + + /* Initialize the Rx Buffer descriptors */ + for (i = 0; i < PKTBUFSRX; i++) { + rx_dp = &cdmac_bd.rx[i]; + memset(rx_dp, 0, sizeof(*rx_dp)); + rx_dp->next_p = rx_dp; + rx_dp->buf_len = PKTSIZE_ALIGN; + rx_dp->phys_buf_p = (u8 *)net_rx_packets[i]; + flush_cache((u32)rx_dp->phys_buf_p, PKTSIZE_ALIGN); + } + flush_cache((u32)cdmac_bd.rx, sizeof(cdmac_bd.rx)); + + /* Initialize the TX Buffer Descriptors */ + for (i = 0; i < TX_BUF_CNT; i++) { + tx_dp = &cdmac_bd.tx[i]; + memset(tx_dp, 0, sizeof(*tx_dp)); + tx_dp->next_p = tx_dp; + } + flush_cache((u32)cdmac_bd.tx, sizeof(cdmac_bd.tx)); + + /* Reset index counter to the Rx and Tx Buffer descriptors */ + rx_idx = tx_idx = 0; + + /* initial Rx DMA start by writing to respective TAILDESC_PTR */ + ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + + return 0; +} + +int ll_temac_halt_sdma(struct eth_device *dev) +{ + unsigned timeout = 50; /* 1usec * 50 = 50usec */ + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + /* + * Soft reset the DMA + * + * Quote from MPMC documentation: Writing a 1 to this field + * forces the DMA engine to shutdown and reset itself. After + * setting this bit, software must poll it until the bit is + * cleared by the DMA. This indicates that the reset process + * is done and the pipeline has been flushed. + */ + ll_temac->out32(ra[DMA_CONTROL_REG], DMA_CONTROL_RESET); + while (timeout && (ll_temac->in32(ra[DMA_CONTROL_REG]) + & DMA_CONTROL_RESET)) { + timeout--; + udelay(1); + } + + if (!timeout) { + printf("%s: Timeout\n", __func__); + return -1; + } + + return 0; +} + +int ll_temac_reset_sdma(struct eth_device *dev) +{ + u32 r; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + /* Soft reset the DMA. */ + if (ll_temac_halt_sdma(dev)) + return -1; + + /* Now clear the interrupts. */ + r = ll_temac->in32(ra[TX_CHNL_CTRL]); + r &= ~CHNL_CTRL_IRQ_MASK; + ll_temac->out32(ra[TX_CHNL_CTRL], r); + + r = ll_temac->in32(ra[RX_CHNL_CTRL]); + r &= ~CHNL_CTRL_IRQ_MASK; + ll_temac->out32(ra[RX_CHNL_CTRL], r); + + /* Now ACK pending IRQs. */ + ll_temac->out32(ra[TX_IRQ_REG], IRQ_REG_IRQ_MASK); + ll_temac->out32(ra[RX_IRQ_REG], IRQ_REG_IRQ_MASK); + + /* Set tail-ptr mode, disable errors for both channels. */ + ll_temac->out32(ra[DMA_CONTROL_REG], + /* Enable use of tail pointer register */ + DMA_CONTROL_TPE | + /* Disable error when 2 or 4 bit coalesce cnt overfl */ + DMA_CONTROL_RXOCEID | + /* Disable error when 2 or 4 bit coalesce cnt overfl */ + DMA_CONTROL_TXOCEID); + + return 0; +} + +int ll_temac_recv_sdma(struct eth_device *dev) +{ + int length, pb_idx; + struct cdmac_bd *rx_dp = &cdmac_bd.rx[rx_idx]; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + if (ll_temac_sdma_error(dev)) { + + if (ll_temac_reset_sdma(dev)) + return -1; + + ll_temac_init_sdma(dev); + } + + flush_cache((u32)rx_dp, sizeof(*rx_dp)); + + if (!(rx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED)) + return 0; + + if (rx_dp->sca.stctrl & (CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP)) { + pb_idx = rx_idx; + length = rx_dp->sca.app[4] & CDMAC_BD_APP4_RXBYTECNT_MASK; + } else { + pb_idx = -1; + length = 0; + printf("%s: Got part of package, unsupported (%x)\n", + __func__, rx_dp->sca.stctrl); + } + + /* flip the buffer */ + flush_cache((u32)rx_dp->phys_buf_p, length); + + /* reset the current descriptor */ + rx_dp->sca.stctrl = 0; + rx_dp->sca.app[4] = 0; + flush_cache((u32)rx_dp, sizeof(*rx_dp)); + + /* Find next empty buffer descriptor, preparation for next iteration */ + rx_idx = (rx_idx + 1) % PKTBUFSRX; + rx_dp = &cdmac_bd.rx[rx_idx]; + flush_cache((u32)rx_dp, sizeof(*rx_dp)); + + /* DMA start by writing to respective TAILDESC_PTR */ + ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]); + + if (length > 0 && pb_idx != -1) + net_process_received_packet(net_rx_packets[pb_idx], length); + + return 0; +} + +int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length) +{ + unsigned timeout = 50; /* 1usec * 50 = 50usec */ + struct cdmac_bd *tx_dp = &cdmac_bd.tx[tx_idx]; + struct ll_temac *ll_temac = dev->priv; + phys_addr_t *ra = ll_temac->sdma_reg_addr; + + if (ll_temac_sdma_error(dev)) { + + if (ll_temac_reset_sdma(dev)) + return -1; + + ll_temac_init_sdma(dev); + } + + tx_dp->phys_buf_p = (u8 *)packet; + tx_dp->buf_len = length; + tx_dp->sca.stctrl = CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP | + CDMAC_BD_STCTRL_STOP_ON_END; + + flush_cache((u32)packet, length); + flush_cache((u32)tx_dp, sizeof(*tx_dp)); + + /* DMA start by writing to respective TAILDESC_PTR */ + ll_temac->out32(ra[TX_CURDESC_PTR], (int)tx_dp); + ll_temac->out32(ra[TX_TAILDESC_PTR], (int)tx_dp); + + /* Find next empty buffer descriptor, preparation for next iteration */ + tx_idx = (tx_idx + 1) % TX_BUF_CNT; + tx_dp = &cdmac_bd.tx[tx_idx]; + + do { + flush_cache((u32)tx_dp, sizeof(*tx_dp)); + udelay(1); + } while (timeout-- && !(tx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED)); + + if (!timeout) { + printf("%s: Timeout\n", __func__); + return -1; + } + + return 0; +} diff --git a/drivers/net/xilinx_ll_temac_sdma.h b/drivers/net/xilinx_ll_temac_sdma.h new file mode 100644 index 00000000000..41659c0eeba --- /dev/null +++ b/drivers/net/xilinx_ll_temac_sdma.h @@ -0,0 +1,277 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * SDMA sub-controller interface + * + * Copyright (C) 2011 - 2012 Stephan Linz + * Copyright (C) 2008 - 2011 Michal Simek + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * SPDX-License-Identifier: GPL-2.0+ + * + * [0]: http://www.xilinx.com/support/documentation + * + * [S]: [0]/ip_documentation/xps_ll_temac.pdf + * [A]: [0]/application_notes/xapp1041.pdf + */ +#ifndef _XILINX_LL_TEMAC_SDMA_ +#define _XILINX_LL_TEMAC_SDMA_ + +#include + +#include +#include + +#include + +#if !defined(__BIG_ENDIAN) +# error LL_TEMAC requires big endianess +#endif + +/* + * DMA Buffer Descriptor for CDMAC + * + * Used for data connection from and to (Rx/Tx) the LocalLink (LL) TEMAC via + * the Communications Direct Memory Access Controller (CDMAC) -- one for each. + * + * overview: + * ftp://ftp.xilinx.com/pub/documentation/misc/mpmc_getting_started.pdf + * + * [1]: [0]/ip_documentation/mpmc.pdf + * page 140, DMA Operation Descriptors + * + * [2]: [0]/user_guides/ug200.pdf + * page 229, DMA Controller -- Descriptor Format + * + * [3]: [0]/ip_documentation/xps_ll_temac.pdf + * page 72, Transmit LocalLink Frame Format + * page 73, Receive LocalLink Frame Format + */ +struct cdmac_bd { + struct cdmac_bd *next_p; /* Next Descriptor Pointer */ + u8 *phys_buf_p; /* Buffer Address */ + u32 buf_len; /* Buffer Length */ + union { + u8 stctrl; /* Status/Control the DMA transfer */ + u32 app[5]; /* application specific data */ + } __packed __aligned(1) sca; +}; + +/* CDMAC Descriptor Status and Control (stctrl), [1] p140, [2] p230 */ +#define CDMAC_BD_STCTRL_ERROR (1 << 7) +#define CDMAC_BD_STCTRL_IRQ_ON_END (1 << 6) +#define CDMAC_BD_STCTRL_STOP_ON_END (1 << 5) +#define CDMAC_BD_STCTRL_COMPLETED (1 << 4) +#define CDMAC_BD_STCTRL_SOP (1 << 3) +#define CDMAC_BD_STCTRL_EOP (1 << 2) +#define CDMAC_BD_STCTRL_DMACHBUSY (1 << 1) + +/* CDMAC Descriptor APP0: Transmit LocalLink Footer Word 3, [3] p72 */ +#define CDMAC_BD_APP0_TXCSCNTRL (1 << 0) + +/* CDMAC Descriptor APP1: Transmit LocalLink Footer Word 4, [3] p73 */ +#define CDMAC_BD_APP1_TXCSBEGIN_POS 16 +#define CDMAC_BD_APP1_TXCSBEGIN_MASK (0xFFFF << CDMAC_BD_APP1_TXCSBEGIN_POS) +#define CDMAC_BD_APP1_TXCSINSERT_POS 0 +#define CDMAC_BD_APP1_TXCSINSERT_MASK (0xFFFF << CDMAC_BD_APP1_TXCSINSERT_POS) + +/* CDMAC Descriptor APP2: Transmit LocalLink Footer Word 5, [3] p73 */ +#define CDMAC_BD_APP2_TXCSINIT_POS 0 +#define CDMAC_BD_APP2_TXCSINIT_MASK (0xFFFF << CDMAC_BD_APP2_TXCSINIT_POS) + +/* CDMAC Descriptor APP0: Receive LocalLink Footer Word 3, [3] p73 */ +#define CDMAC_BD_APP0_MADDRU_POS 0 +#define CDMAC_BD_APP0_MADDRU_MASK (0xFFFF << CDMAC_BD_APP0_MADDRU_POS) + +/* CDMAC Descriptor APP1: Receive LocalLink Footer Word 4, [3] p74 */ +#define CDMAC_BD_APP1_MADDRL_POS 0 +#define CDMAC_BD_APP1_MADDRL_MASK (~0UL << CDMAC_BD_APP1_MADDRL_POS) + +/* CDMAC Descriptor APP2: Receive LocalLink Footer Word 5, [3] p74 */ +#define CDMAC_BD_APP2_BCAST_FRAME (1 << 2) +#define CDMAC_BD_APP2_IPC_MCAST_FRAME (1 << 1) +#define CDMAC_BD_APP2_MAC_MCAST_FRAME (1 << 0) + +/* CDMAC Descriptor APP3: Receive LocalLink Footer Word 6, [3] p74 */ +#define CDMAC_BD_APP3_TLTPID_POS 16 +#define CDMAC_BD_APP3_TLTPID_MASK (0xFFFF << CDMAC_BD_APP3_TLTPID_POS) +#define CDMAC_BD_APP3_RXCSRAW_POS 0 +#define CDMAC_BD_APP3_RXCSRAW_MASK (0xFFFF << CDMAC_BD_APP3_RXCSRAW_POS) + +/* CDMAC Descriptor APP4: Receive LocalLink Footer Word 7, [3] p74 */ +#define CDMAC_BD_APP4_VLANTAG_POS 16 +#define CDMAC_BD_APP4_VLANTAG_MASK (0xFFFF << CDMAC_BD_APP4_VLANTAG_POS) +#define CDMAC_BD_APP4_RXBYTECNT_POS 0 +#define CDMAC_BD_APP4_RXBYTECNT_MASK (0x3FFF << CDMAC_BD_APP4_RXBYTECNT_POS) + +/* + * SDMA Register Definition + * + * [0]: http://www.xilinx.com/support/documentation + * + * [1]: [0]/ip_documentation/mpmc.pdf + * page 54, SDMA Register Summary + * page 160, SDMA Registers + * + * [2]: [0]/user_guides/ug200.pdf + * page 244, DMA Controller -- Programming Interface and Registers + */ +#define SDMA_CTRL_REGTYPE u32 +#define SDMA_CTRL_REGSIZE sizeof(SDMA_CTRL_REGTYPE) +struct sdma_ctrl { + /* Transmit Registers */ + SDMA_CTRL_REGTYPE tx_nxtdesc_ptr; /* TX Next Description Pointer */ + SDMA_CTRL_REGTYPE tx_curbuf_addr; /* TX Current Buffer Address */ + SDMA_CTRL_REGTYPE tx_curbuf_length; /* TX Current Buffer Length */ + SDMA_CTRL_REGTYPE tx_curdesc_ptr; /* TX Current Descriptor Pointer */ + SDMA_CTRL_REGTYPE tx_taildesc_ptr; /* TX Tail Descriptor Pointer */ + SDMA_CTRL_REGTYPE tx_chnl_ctrl; /* TX Channel Control */ + SDMA_CTRL_REGTYPE tx_irq_reg; /* TX Interrupt Register */ + SDMA_CTRL_REGTYPE tx_chnl_sts; /* TX Status Register */ + /* Receive Registers */ + SDMA_CTRL_REGTYPE rx_nxtdesc_ptr; /* RX Next Descriptor Pointer */ + SDMA_CTRL_REGTYPE rx_curbuf_addr; /* RX Current Buffer Address */ + SDMA_CTRL_REGTYPE rx_curbuf_length; /* RX Current Buffer Length */ + SDMA_CTRL_REGTYPE rx_curdesc_ptr; /* RX Current Descriptor Pointer */ + SDMA_CTRL_REGTYPE rx_taildesc_ptr; /* RX Tail Descriptor Pointer */ + SDMA_CTRL_REGTYPE rx_chnl_ctrl; /* RX Channel Control */ + SDMA_CTRL_REGTYPE rx_irq_reg; /* RX Interrupt Register */ + SDMA_CTRL_REGTYPE rx_chnl_sts; /* RX Status Register */ + /* Control Registers */ + SDMA_CTRL_REGTYPE dma_control_reg; /* DMA Control Register */ +}; + +#define SDMA_CTRL_REGNUMS sizeof(struct sdma_ctrl)/SDMA_CTRL_REGSIZE + +/* + * DMAC Register Index Enumeration + * + * [2]: http://www.xilinx.com/support/documentation/user_guides/ug200.pdf + * page 244, DMA Controller -- Programming Interface and Registers + */ +enum dmac_ctrl { + /* Transmit Registers */ + TX_NXTDESC_PTR = 0, /* TX Next Description Pointer */ + TX_CURBUF_ADDR, /* TX Current Buffer Address */ + TX_CURBUF_LENGTH, /* TX Current Buffer Length */ + TX_CURDESC_PTR, /* TX Current Descriptor Pointer */ + TX_TAILDESC_PTR, /* TX Tail Descriptor Pointer */ + TX_CHNL_CTRL, /* TX Channel Control */ + TX_IRQ_REG, /* TX Interrupt Register */ + TX_CHNL_STS, /* TX Status Register */ + /* Receive Registers */ + RX_NXTDESC_PTR, /* RX Next Descriptor Pointer */ + RX_CURBUF_ADDR, /* RX Current Buffer Address */ + RX_CURBUF_LENGTH, /* RX Current Buffer Length */ + RX_CURDESC_PTR, /* RX Current Descriptor Pointer */ + RX_TAILDESC_PTR, /* RX Tail Descriptor Pointer */ + RX_CHNL_CTRL, /* RX Channel Control */ + RX_IRQ_REG, /* RX Interrupt Register */ + RX_CHNL_STS, /* RX Status Register */ + /* Control Registers */ + DMA_CONTROL_REG /* DMA Control Register */ +}; + +/* Rx/Tx Channel Control Register (*_chnl_ctrl), [1] p163, [2] p246/p252 */ +#define CHNL_CTRL_ITO_POS 24 +#define CHNL_CTRL_ITO_MASK (0xFF << CHNL_CTRL_ITO_POS) +#define CHNL_CTRL_IC_POS 16 +#define CHNL_CTRL_IC_MASK (0xFF << CHNL_CTRL_IC_POS) +#define CHNL_CTRL_MSBADDR_POS 12 +#define CHNL_CTRL_MSBADDR_MASK (0xF << CHNL_CTRL_MSBADDR_POS) +#define CHNL_CTRL_AME (1 << 11) +#define CHNL_CTRL_OBWC (1 << 10) +#define CHNL_CTRL_IOE (1 << 9) +#define CHNL_CTRL_LIC (1 << 8) +#define CHNL_CTRL_IE (1 << 7) +#define CHNL_CTRL_IEE (1 << 2) +#define CHNL_CTRL_IDE (1 << 1) +#define CHNL_CTRL_ICE (1 << 0) + +/* All interrupt enable bits */ +#define CHNL_CTRL_IRQ_MASK (CHNL_CTRL_IE | \ + CHNL_CTRL_IEE | \ + CHNL_CTRL_IDE | \ + CHNL_CTRL_ICE) + +/* Rx/Tx Interrupt Status Register (*_irq_reg), [1] p164, [2] p247/p253 */ +#define IRQ_REG_DTV_POS 24 +#define IRQ_REG_DTV_MASK (0xFF << IRQ_REG_DTV_POS) +#define IRQ_REG_CCV_POS 16 +#define IRQ_REG_CCV_MASK (0xFF << IRQ_REG_CCV_POS) +#define IRQ_REG_WRCQ_EMPTY (1 << 14) +#define IRQ_REG_CIC_POS 10 +#define IRQ_REG_CIC_MASK (0xF << IRQ_REG_CIC_POS) +#define IRQ_REG_DIC_POS 8 +#define IRQ_REG_DIC_MASK (3 << 8) +#define IRQ_REG_PLB_RD_NMI (1 << 4) +#define IRQ_REG_PLB_WR_NMI (1 << 3) +#define IRQ_REG_EI (1 << 2) +#define IRQ_REG_DI (1 << 1) +#define IRQ_REG_CI (1 << 0) + +/* All interrupt bits */ +#define IRQ_REG_IRQ_MASK (IRQ_REG_PLB_RD_NMI | \ + IRQ_REG_PLB_WR_NMI | \ + IRQ_REG_EI | IRQ_REG_DI | IRQ_REG_CI) + +/* Rx/Tx Channel Status Register (*_chnl_sts), [1] p165, [2] p249/p255 */ +#define CHNL_STS_ERROR_TAIL (1 << 21) +#define CHNL_STS_ERROR_CMP (1 << 20) +#define CHNL_STS_ERROR_ADDR (1 << 19) +#define CHNL_STS_ERROR_NXTP (1 << 18) +#define CHNL_STS_ERROR_CURP (1 << 17) +#define CHNL_STS_ERROR_BSYWR (1 << 16) +#define CHNL_STS_ERROR (1 << 7) +#define CHNL_STS_IOE (1 << 6) +#define CHNL_STS_SOE (1 << 5) +#define CHNL_STS_CMPLT (1 << 4) +#define CHNL_STS_SOP (1 << 3) +#define CHNL_STS_EOP (1 << 2) +#define CHNL_STS_EBUSY (1 << 1) + +/* DMA Control Register (dma_control_reg), [1] p166, [2] p256 */ +#define DMA_CONTROL_PLBED (1 << 5) +#define DMA_CONTROL_RXOCEID (1 << 4) +#define DMA_CONTROL_TXOCEID (1 << 3) +#define DMA_CONTROL_TPE (1 << 2) +#define DMA_CONTROL_RESET (1 << 0) + +#if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) + +/* Xilinx Device Control Register (DCR) in/out accessors */ +unsigned ll_temac_xldcr_in32(phys_addr_t addr); +void ll_temac_xldcr_out32(phys_addr_t addr, unsigned value); + +/* collect all register addresses for Xilinx DCR in/out accessors */ +void ll_temac_collect_xldcr_sdma_reg_addr(struct eth_device *dev); + +#endif /* CONFIG_XILINX_440 || CONFIG_XILINX_405 */ + +/* Xilinx Processor Local Bus (PLB) in/out accessors */ +unsigned ll_temac_xlplb_in32(phys_addr_t base); +void ll_temac_xlplb_out32(phys_addr_t base, unsigned value); + +/* collect all register addresses for Xilinx PLB in/out accessors */ +void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev); + +/* initialize both Rx/Tx buffer descriptors */ +int ll_temac_init_sdma(struct eth_device *dev); + +/* halt both Rx/Tx transfers */ +int ll_temac_halt_sdma(struct eth_device *dev); + +/* reset SDMA and IRQ, disable interrupts and errors */ +int ll_temac_reset_sdma(struct eth_device *dev); + +/* receive buffered data from SDMA (polling ISR) */ +int ll_temac_recv_sdma(struct eth_device *dev); + +/* send buffered data to SDMA */ +int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length); + +#endif /* _XILINX_LL_TEMAC_SDMA_ */ diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h new file mode 100644 index 00000000000..f1cbc8eca72 --- /dev/null +++ b/include/configs/fx12mm.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2008 + * + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com + * + * Georg Schardt + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, + * see http://www.em.avnet.com + */ + +#ifndef __CONFIG_FX12_H +#define __CONFIG_FX12_H + +#include "../board/avnet/fx12mm/xparameters.h" + +/* cmd config */ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD + +/* sdram */ +#define CONFIG_SYS_SDRAM_SIZE_MB 64 + +/* environment */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_SYS_ENV_OFFSET 0xA0000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET) +#define CONFIG_ENV_OVERWRITE 1 + +/*Misc*/ +#define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and running;" + +/*Flash*/ +#define CONFIG_SYS_FLASH_SIZE (4*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define MTDIDS_DEFAULT "nor0=fx12mm-flash" +#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)" + +#include "configs/xilinx-ppc405.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/ml507.h b/include/configs/ml507.h new file mode 100644 index 00000000000..b9ecb091b61 --- /dev/null +++ b/include/configs/ml507.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*CPU*/ +#define CONFIG_440 1 +#define CONFIG_XILINX_ML507 1 +#include "../board/xilinx/ml507/xparameters.h" + +/*Mem Map*/ +#define CONFIG_SYS_SDRAM_SIZE_MB 256 + +/*Env*/ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x340000 +#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) + +/*Misc*/ +#define CONFIG_SYS_PROMPT "ml507:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Flash*/ +#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 259 +#define MTDIDS_DEFAULT "nor0=ml507-flash" +#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" + +/*Generic Configs*/ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/v5fx30teval.h b/include/configs/v5fx30teval.h new file mode 100644 index 00000000000..f30a0904a3f --- /dev/null +++ b/include/configs/v5fx30teval.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*CPU*/ +#define CONFIG_440 1 +#define CONFIG_XILINX_ML507 1 +#include "../board/avnet/v5fx30teval/xparameters.h" + +/*Mem Map*/ +#define CONFIG_SYS_SDRAM_SIZE_MB 64 + +/*Env*/ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x1A0000 +#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) + +/*Misc*/ +#define CONFIG_SYS_PROMPT "v5fx30t:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Flash*/ +#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define MTDIDS_DEFAULT "nor0=v5fx30t-flash" +#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)" + +/*Generic Configs*/ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h index f7aa182062a..75b119f8556 100644 --- a/include/configs/xilinx-ppc405-generic.h +++ b/include/configs/xilinx-ppc405-generic.h @@ -1,277 +1,42 @@ /* - * (C) Copyright 2007-2010 Michal Simek * - * Michal SIMEK + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * (C) Copyright 2008 + * Georg Schardt * * SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_GEN_H +#define __CONFIG_GEN_H #include "../board/xilinx/ppc405-generic/xparameters.h" -/* cpu parameter */ -#define CONFIG_405 1 -#define CONFIG_4xx 1 -#define CONFIG_XILINX_405 1 - -/* PPC-specific memory layout */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/*Stack*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0x800000/* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ - - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*Speed*/ -#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ - -/* Common PPC-specific settings */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 - /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 - /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_EXTBDINFO 1 - /* Extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 - /* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - /* Initial Memory map for Linux */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* use serial multi for all serial devices */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -#ifdef XILINX_UARTLITE_BASEADDR -# define CONFIG_XILINX_UARTLITE -# if defined(XILINX_UARTLITE_BAUDRATE) -# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -# endif -#endif - -#if XILINX_UART16550_BASEADDR -# define CONFIG_SYS_NS16550 1 -# define CONFIG_SYS_NS16550_SERIAL -# define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) -# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ - -# if defined(__MICROBLAZEEL__) -# define CONFIG_SYS_NS16550_REG_SIZE -4 -# else -# define CONFIG_SYS_NS16550_REG_SIZE 4 -# endif - -/* CONS_INDEX for system with uartlite only mustn't define CONFIG_CONS_INDEX - * u-boot BSP generates CONFIG_CONS_INDEX for system with several uart16550 */ -# if !defined(CONFIG_CONS_INDEX) -# define CONFIG_CONS_INDEX 1 -# endif -#endif - -#if !defined(CONFIG_BAUDRATE) - #define CONFIG_BAUDRATE 115200 -#endif - -#undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) - #define CONFIG_XILINX_EMACLITE 1 - #define CONFIG_SYS_ENET -#endif -#if defined(XILINX_LLTEMAC_BASEADDR) - #define CONFIG_XILINX_LL_TEMAC 1 - #define CONFIG_SYS_ENET -#endif - -#undef ET_DEBUG - - -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR - #define CONFIG_SYS_INTC_0 1 - #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR - #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#ifdef XILINX_TIMER_BASEADDR - #if (XILINX_TIMER_IRQ != -1) - #define CONFIG_SYS_TIMER_0 1 - #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR - #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ - #define FREQUENCE XILINX_CLOCK_FREQ - #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) - #endif -#else -# error Please setup TIMER in BSP -#endif - -/* - * memory layout - Example - * TEXT_BASE = 0x1200_0000; - * CONFIG_SYS_SRAM_BASE = 0x1000_0000; - * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; - * - * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 - * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 - * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 - * - * 0x1000_0000 CONFIG_SYS_SDRAM_BASE - * FREE - * 0x1200_0000 TEXT_BASE - * U-BOOT code - * 0x1202_0000 - * FREE - * - * STACK - * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE - * MALLOC_AREA 256kB Alloc - * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE - * MONITOR_CODE 256kB Env - * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd - * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - */ - -/* ddr sdram - main memory */ -#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE - -#if defined(XILINX_FLASH_START) /* Parallel Flash */ - #define FLASH - #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START - #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE - #define CONFIG_SYS_FLASH_CFI 1 - #define CONFIG_FLASH_CFI_DRIVER 1 - #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ - - /* Assume env is in flash, this may be undone lower down */ - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - - #define CONFIG_SYS_FLASH_PROTECTION - - #define CONFIG_ENV_ADDR XILINX_FLASH_START - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#else /* No flash memory at all */ - /* ENV in RAM */ - #define RAMENV - #define CONFIG_SYS_NO_FLASH 1 - - #define CONFIG_ENV_IS_NOWHERE 1 - #undef CONFIG_ENV_IS_IN_FLASH - #undef CONFIG_ENV_IS_IN_SPI_FLASH - #define CONFIG_ENV_SIZE 0x1000 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -/* FIXME: hack for zynq */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ECHO - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_JFFS2 -#ifndef CONFIG_SYS_ENET - #undef CONFIG_CMD_NET - #undef CONFIG_NET_MULTI -#else - #define CONFIG_CMD_PING - #define CONFIG_NET_MULTI -#endif - -#if defined(FLASH) - #define CONFIG_CMD_FLASH - #define CONFIG_CMD_IMLS -#else - #undef CONFIG_CMD_IMLS - #undef CONFIG_CMD_FLASH - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_SAVES -#endif - -#if !defined(RAMENV) - #define CONFIG_CMD_SAVEENV - #define CONFIG_CMD_SAVES -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */ - -#define CONFIG_BOOTDELAY 4 -/* Don't define BOOTARGS, we get it from the DTB chosen fragment */ -#undef CONFIG_BOOTARGS -#define CONFIG_HOSTNAME XILINX_BOARD_NAME - -#define CONFIG_BOOTCOMMAND "" - -/* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ -#define CONFIG_IPADDR 192.168.10.90 -#define CONFIG_SERVERIP 192.168.10.101 -#define CONFIG_ETHADDR 00:0a:35:00:92:d4 -#define CONFIG_BOOTP_SERVERIP - -#define CONFIG_CMDLINE_EDITING - -/* Use the HUSH parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 - -#if defined(CONFIG_XILINX_LL_TEMAC) -# define CONFIG_MII 1 -# define CONFIG_CMD_MII 1 -# define CONFIG_PHY_GIGE 1 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -# define CONFIG_PHYLIB 1 -# define CONFIG_PHY_ATHEROS 1 -# define CONFIG_PHY_BROADCOM 1 -# define CONFIG_PHY_DAVICOM 1 -# define CONFIG_PHY_LXT 1 -# define CONFIG_PHY_MARVELL 1 -# define CONFIG_PHY_MICREL 1 -# define CONFIG_PHY_NATSEMI 1 -# define CONFIG_PHY_REALTEK 1 -# define CONFIG_PHY_VITESSE 1 -#else -# undef CONFIG_MII -# undef CONFIG_CMD_MII -# undef CONFIG_PHYLIB -#endif - -#endif /* __CONFIG_H */ +/* sdram */ +#define CONFIG_SYS_SDRAM_SIZE_MB 256 + +/* environment */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_SYS_ENV_OFFSET 0x3F0000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET) +#define CONFIG_ENV_OVERWRITE 1 + +/*Misc*/ +#define CONFIG_SYS_PROMPT "xlx-ppc405:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Flash*/ +#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define MTDIDS_DEFAULT "nor0=ppc405-flash" +#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)" + +#include +#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h new file mode 100644 index 00000000000..a0151fe8f4c --- /dev/null +++ b/include/configs/xilinx-ppc405.h @@ -0,0 +1,22 @@ +/* + * + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * (C) Copyright 2008 + * Georg Schardt + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* cpu parameter */ +#define CONFIG_405 1 +#define CONFIG_XILINX_405 1 + +#include + +#endif diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h index 7799ae49abd..8e684151efe 100644 --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@ -1,282 +1,39 @@ /* - * (C) Copyright 2007-2010 Michal Simek - * - * Michal SIMEK - * + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ * SPDX-License-Identifier: GPL-2.0+ - */ +*/ #ifndef __CONFIG_H #define __CONFIG_H +/*CPU*/ +#define CONFIG_440 1 +#define CONFIG_XILINX_PPC440_GENERIC 1 #include "../board/xilinx/ppc440-generic/xparameters.h" -/* cpu parameter */ -#define CONFIG_4xx 1 -#define CONFIG_440 1 -#define CONFIG_XILINX_440 1 -#define CONFIG_XILINX_440_GENERIC 1 +/*Mem Map*/ +#define CONFIG_SYS_SDRAM_SIZE_MB 256 -/* Gross XPAR_ hackery */ -#define XPAR_INTC_0_BASEADDR XILINX_INTC_BASEADDR -#define XPAR_INTC_MAX_NUM_INTR_INPUTS XILINX_INTC_NUM_INTR_INPUTS +/*Env*/ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x340000 +#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) -/* PPC-specific memory layout */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) +/*Misc*/ +#define CONFIG_SYS_PROMPT "board:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" -/*Stack*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0x800000/* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +/*Flash*/ +#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 259 +#define MTDIDS_DEFAULT "nor0=ml507-flash" +#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" -/*Speed*/ -#define CONFIG_SYS_CLK_FREQ XILINX_CLOCK_FREQ +/*Generic Configs*/ +#include -/* Common PPC-specific settings */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 - /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 - /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_EXTBDINFO 1 - /* Extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 - /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) - /* Initial Memory map for Linux */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* use serial multi for all serial devices */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 - -#ifdef XILINX_UARTLITE_BASEADDR -# define CONFIG_XILINX_UARTLITE -# if defined(XILINX_UARTLITE_BAUDRATE) -# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -# endif -#endif - -#if XILINX_UART16550_BASEADDR -# define CONFIG_SYS_NS16550 1 -# define CONFIG_SYS_NS16550_SERIAL -# define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) -# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ - -# if defined(__MICROBLAZEEL__) -# define CONFIG_SYS_NS16550_REG_SIZE -4 -# else -# define CONFIG_SYS_NS16550_REG_SIZE 4 -# endif - -/* CONS_INDEX for system with uartlite only mustn't define CONFIG_CONS_INDEX - * u-boot BSP generates CONFIG_CONS_INDEX for system with several uart16550 */ -# if !defined(CONFIG_CONS_INDEX) -# define CONFIG_CONS_INDEX 1 -# endif -#endif - -#if !defined(CONFIG_BAUDRATE) - #define CONFIG_BAUDRATE 115200 -#endif - -#undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) - #define CONFIG_XILINX_EMACLITE 1 - #define CONFIG_SYS_ENET -#endif -#if defined(XILINX_LLTEMAC_BASEADDR) - #define CONFIG_XILINX_LL_TEMAC 1 - #define CONFIG_SYS_ENET -#endif - -#undef ET_DEBUG - - -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR - #define CONFIG_SYS_INTC_0 1 - #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR - #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#ifdef XILINX_TIMER_BASEADDR - #if (XILINX_TIMER_IRQ != -1) - #define CONFIG_SYS_TIMER_0 1 - #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR - #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ - #define FREQUENCE XILINX_CLOCK_FREQ - #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) - #endif -#else -# error Please setup TIMER in BSP -#endif - -/* - * memory layout - Example - * TEXT_BASE = 0x1200_0000; - * CONFIG_SYS_SRAM_BASE = 0x1000_0000; - * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; - * - * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 - * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 - * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 - * - * 0x1000_0000 CONFIG_SYS_SDRAM_BASE - * FREE - * 0x1200_0000 TEXT_BASE - * U-BOOT code - * 0x1202_0000 - * FREE - * - * STACK - * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE - * MALLOC_AREA 256kB Alloc - * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE - * MONITOR_CODE 256kB Env - * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd - * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - */ - -/* ddr sdram - main memory */ -#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE - -#if defined(XILINX_FLASH_START) /* Parallel Flash */ - #define FLASH - #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START - #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE - #define CONFIG_SYS_FLASH_CFI 1 - #define CONFIG_FLASH_CFI_DRIVER 1 - #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ - - /* Assume env is in flash, this may be undone lower down */ - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - - #define CONFIG_SYS_FLASH_PROTECTION - - #define CONFIG_ENV_ADDR XILINX_FLASH_START - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#else /* No flash memory at all */ - /* ENV in RAM */ - #define RAMENV - #define CONFIG_SYS_NO_FLASH 1 - - #define CONFIG_ENV_IS_NOWHERE 1 - #undef CONFIG_ENV_IS_IN_FLASH - #undef CONFIG_ENV_IS_IN_SPI_FLASH - #define CONFIG_ENV_SIZE 0x1000 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -/* FIXME: hack for zynq */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ECHO - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_JFFS2 -#ifndef CONFIG_SYS_ENET - #undef CONFIG_CMD_NET - #undef CONFIG_NET_MULTI -#else - #define CONFIG_CMD_PING - #define CONFIG_NET_MULTI -#endif - -#if defined(FLASH) - #define CONFIG_CMD_FLASH - #define CONFIG_CMD_IMLS -#else - #undef CONFIG_CMD_IMLS - #undef CONFIG_CMD_FLASH - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_SAVES -#endif - -#if !defined(RAMENV) - #define CONFIG_CMD_SAVEENV - #define CONFIG_CMD_SAVES -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */ - -#define CONFIG_BOOTDELAY 4 -/* Don't define BOOTARGS, we get it from the DTB chosen fragment */ -#undef CONFIG_BOOTARGS -#define CONFIG_HOSTNAME XILINX_BOARD_NAME - -#define CONFIG_BOOTCOMMAND "" - -/* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ -#define CONFIG_IPADDR 192.168.10.90 -#define CONFIG_SERVERIP 192.168.10.101 -#define CONFIG_ETHADDR 00:0a:35:00:92:d4 -#define CONFIG_BOOTP_SERVERIP - -#define CONFIG_CMDLINE_EDITING - -/* Use the HUSH parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 - -#if defined(CONFIG_XILINX_LL_TEMAC) -# define CONFIG_MII 1 -# define CONFIG_CMD_MII 1 -# define CONFIG_PHY_GIGE 1 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -# define CONFIG_PHYLIB 1 -# define CONFIG_PHY_ATHEROS 1 -# define CONFIG_PHY_BROADCOM 1 -# define CONFIG_PHY_DAVICOM 1 -# define CONFIG_PHY_LXT 1 -# define CONFIG_PHY_MARVELL 1 -# define CONFIG_PHY_MICREL 1 -# define CONFIG_PHY_NATSEMI 1 -# define CONFIG_PHY_REALTEK 1 -# define CONFIG_PHY_VITESSE 1 -#else -# undef CONFIG_MII -# undef CONFIG_CMD_MII -# undef CONFIG_PHYLIB -#endif - -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/netdev.h b/include/netdev.h index 386b2780825..662d1735db0 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -89,8 +89,8 @@ int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, int xilinx_emaclite_of_init(const void *blob); int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); -int xilinx_ll_temac_initialize(bd_t *bis, unsigned long base_addr, - int mode, unsigned long ctrl); +int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, + unsigned long ctrl_addr); int zynq_gem_of_init(const void *blob); int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, int phy_addr, u32 emio); -- 2.47.3