From d76e20791b68b0edc2640e21dbc7847cba7e0ffd Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella Date: Thu, 11 Sep 2025 10:49:39 -0300 Subject: [PATCH] powerpc: Consolidate atomic-machine.h The __HAVE_64B_ATOMICS can be define based on __WORDSIZE, and the __ARCH_ACQ_INSTR, MUTEX_HINT_*, and barriers definition are defined by the target cpu. Reviewed-by: Wilco Dijkstra --- sysdeps/powerpc/atomic-machine.h | 50 ++++++++++++----- sysdeps/powerpc/powerpc32/atomic-machine.h | 65 ---------------------- sysdeps/powerpc/powerpc64/atomic-machine.h | 53 ------------------ 3 files changed, 36 insertions(+), 132 deletions(-) delete mode 100644 sysdeps/powerpc/powerpc32/atomic-machine.h delete mode 100644 sysdeps/powerpc/powerpc64/atomic-machine.h diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h index 6f63c38e3d..7291facf47 100644 --- a/sysdeps/powerpc/atomic-machine.h +++ b/sysdeps/powerpc/atomic-machine.h @@ -16,25 +16,47 @@ License along with the GNU C Library; if not, see . */ -/* - * Never include sysdeps/powerpc/atomic-machine.h directly. - * Always use include/atomic.h which will include either - * sysdeps/powerpc/powerpc32/atomic-machine.h - * or - * sysdeps/powerpc/powerpc64/atomic-machine.h - * as appropriate and which in turn include this file. - */ +#ifndef _POWERPC_ATOMIC_MACHINE_H +#define _POWERPC_ATOMIC_MACHINE_H 1 -#define __ARCH_ACQ_INSTR "isync" -#ifndef __ARCH_REL_INSTR -# define __ARCH_REL_INSTR "sync" +#if __WORDSIZE == 64 +# define __HAVE_64B_ATOMICS 1 +#else +# define __HAVE_64B_ATOMICS 0 #endif +#define ATOMIC_EXCHANGE_USES_CAS 1 -#ifndef MUTEX_HINT_ACQ +/* Used on pthread_spin_{try}lock. */ +#define __ARCH_ACQ_INSTR "isync" +#if defined _ARCH_PWR6 || defined _ARCH_PWR6X +# define MUTEX_HINT_ACQ ",1" +# define MUTEX_HINT_REL ",0" +#else # define MUTEX_HINT_ACQ -#endif -#ifndef MUTEX_HINT_REL # define MUTEX_HINT_REL #endif +#ifdef _ARCH_PWR4 +/* + * Newer powerpc64 processors support the new "light weight" sync (lwsync) + * So if the build is using -mcpu=[power4,power5,power5+,970] we can + * safely use lwsync. + */ +# define atomic_read_barrier() __asm ("lwsync" ::: "memory") +/* + * "light weight" sync can also be used for the release barrier. + */ +# define atomic_write_barrier() __asm ("lwsync" ::: "memory") +#else +/* + * Older powerpc32 processors don't support the new "light weight" + * sync (lwsync). So the only safe option is to use normal sync + * for all powerpc32 applications. + */ +# define atomic_read_barrier() __asm ("sync" ::: "memory") +# define atomic_write_barrier() __asm ("sync" ::: "memory") +#endif + #define atomic_full_barrier() __asm ("sync" ::: "memory") + +#endif diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h deleted file mode 100644 index 2e9860cb9d..0000000000 --- a/sysdeps/powerpc/powerpc32/atomic-machine.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Atomic operations. PowerPC32 version. - Copyright (C) 2003-2025 Free Software Foundation, Inc. - This file is part of the GNU C Library. - - The GNU C Library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - The GNU C Library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with the GNU C Library; if not, see - . */ - -/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction. - This is a hint to the hardware to expect additional updates adjacent - to the lock word or not. If we are acquiring a Mutex, the hint - should be true. Otherwise we releasing a Mutex or doing a simple - atomic operation. In that case we don't expect additional updates - adjacent to the lock word after the Store Conditional and the hint - should be false. */ - -#if defined _ARCH_PWR6 || defined _ARCH_PWR6X -# define MUTEX_HINT_ACQ ",1" -# define MUTEX_HINT_REL ",0" -#else -# define MUTEX_HINT_ACQ -# define MUTEX_HINT_REL -#endif - -#define __HAVE_64B_ATOMICS 0 -#define USE_ATOMIC_COMPILER_BUILTINS 1 -#define ATOMIC_EXCHANGE_USES_CAS 1 - -#ifdef _ARCH_PWR4 -/* - * Newer powerpc64 processors support the new "light weight" sync (lwsync) - * So if the build is using -mcpu=[power4,power5,power5+,970] we can - * safely use lwsync. - */ -# define atomic_read_barrier() __asm ("lwsync" ::: "memory") -/* - * "light weight" sync can also be used for the release barrier. - */ -# define __ARCH_REL_INSTR "lwsync" -# define atomic_write_barrier() __asm ("lwsync" ::: "memory") -#else -/* - * Older powerpc32 processors don't support the new "light weight" - * sync (lwsync). So the only safe option is to use normal sync - * for all powerpc32 applications. - */ -# define atomic_read_barrier() __asm ("sync" ::: "memory") -# define atomic_write_barrier() __asm ("sync" ::: "memory") -#endif - -/* - * Include the rest of the atomic ops macros which are common to both - * powerpc32 and powerpc64. - */ -#include_next diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h deleted file mode 100644 index 9ae48a907d..0000000000 --- a/sysdeps/powerpc/powerpc64/atomic-machine.h +++ /dev/null @@ -1,53 +0,0 @@ -/* Atomic operations. PowerPC64 version. - Copyright (C) 2003-2025 Free Software Foundation, Inc. - This file is part of the GNU C Library. - - The GNU C Library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - The GNU C Library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with the GNU C Library; if not, see - . */ - -/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction. - This is a hint to the hardware to expect additional updates adjacent - to the lock word or not. If we are acquiring a Mutex, the hint - should be true. Otherwise we releasing a Mutex or doing a simple - atomic operation. In that case we don't expect additional updates - adjacent to the lock word after the Store Conditional and the hint - should be false. */ - -#if defined _ARCH_PWR6 || defined _ARCH_PWR6X -# define MUTEX_HINT_ACQ ",1" -# define MUTEX_HINT_REL ",0" -#else -# define MUTEX_HINT_ACQ -# define MUTEX_HINT_REL -#endif - -#define __HAVE_64B_ATOMICS 1 -#define USE_ATOMIC_COMPILER_BUILTINS 1 -#define ATOMIC_EXCHANGE_USES_CAS 1 - -/* - * All powerpc64 processors support the new "light weight" sync (lwsync). - */ -#define atomic_read_barrier() __asm ("lwsync" ::: "memory") -/* - * "light weight" sync can also be used for the release barrier. - */ -#define __ARCH_REL_INSTR "lwsync" -#define atomic_write_barrier() __asm ("lwsync" ::: "memory") - -/* - * Include the rest of the atomic ops macros which are common to both - * powerpc32 and powerpc64. - */ -#include_next -- 2.47.3