From e00ad79244eff5181a117214f2b54b478df9b3d7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 24 Apr 2025 06:40:46 +0100 Subject: [PATCH] arm64: dts: renesas: rzg2l-smarc: Enable GPT on carrier board The GPT4 IOs are available on the carrier board's PMOD0 connector (J1). Enable the GPT on the carrier board by adding the GPT pinmux and node on the carrier board dtsi file. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250424054050.28310-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts | 7 +++++++ arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 7 +++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 5 +++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 8 ++++++++ 4 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index 568d49cfe44a6..b36749f94ccbd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -27,6 +27,13 @@ #error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" #endif +/* + * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the + * PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1" + * below. + */ +#define PMOD0_GPT 0 + #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index b3e6016880dda..43c456ffa63cf 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -26,6 +26,13 @@ #error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" #endif +/* + * To enable the GPT pins GTIOC4A(PMOD0_PIN7) and GTIOC4B(PMOD0_PIN10) on the + * PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1" + * below. + */ +#define PMOD0_GPT 0 + #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index e9f244c33d558..2616dbde4dd59 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -38,6 +38,11 @@ line-name = "can1_stb"; }; + gpt_pins: gpt { + pinmux = , /* GTIOC4A */ + ; /* GTIOC4B */ + }; + i2c0_pins: i2c0 { pins = "RIIC0_SDA", "RIIC0_SCL"; input-enable; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 789f7b0b5ebca..b76b55e7f09df 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -104,6 +104,14 @@ }; }; +#if PMOD0_GPT +&gpt { + pinctrl-0 = <&gpt_pins>; + pinctrl-names = "default"; + status = "okay"; +}; +#endif /* PMOD0_GPT */ + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; -- 2.47.3