From e4ab44d8b28db868955d0da5dcadae5ef99a1dff Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 19 Mar 2026 13:40:33 +0200 Subject: [PATCH] drm/i915/wm: Include ddb_y in skl_print_wm_changes() on pre-icl MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Pre-icl doesn't use a separate hardware plane for Y scanout, and instead it's all handled magically by the hardware. We do still need to allocate DDB space for the Y color plane though (PLANE_NV12_BUF_CFG). Include that information in the debugs so that we know where it ended up. On icl+ the equivalent information is dumped as the hardware Y plane's normal ddb allocation. v2: Use prink field width for ddb_name alignment Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260319114034.7093-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_watermark.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 6ad0546c928f6..e9cfbb7c9a77f 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2735,10 +2735,17 @@ skl_print_wm_changes(struct intel_atomic_state *state) old = &old_crtc_state->wm.skl.plane_ddb[plane_id]; new = &new_crtc_state->wm.skl.plane_ddb[plane_id]; - if (skl_ddb_entry_equal(old, new)) + if (!skl_ddb_entry_equal(old, new)) + skl_print_plane_ddb_changes(plane, old, new, "ddb"); + + if (DISPLAY_VER(display) >= 11) continue; - skl_print_plane_ddb_changes(plane, old, new, "ddb"); + old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id]; + new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id]; + + if (!skl_ddb_entry_equal(old, new)) + skl_print_plane_ddb_changes(plane, old, new, "ddb_y"); } for_each_intel_plane_on_crtc(display->drm, crtc, plane) { -- 2.47.3