From e72d63fa0563f8a6e98c10fed3a9ce74dc0536e6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:08 +0200 Subject: [PATCH] arm64: dts: mediatek: mt8183: Migrate to display controller OF graph The display related IPs in MT8183 are flexible and support being interconnected with different instances of DDP IPs forming a full Display Data Path that ends with an actual display output, which is board specific. Add a common graph in the main mt8183.dtsi devicetree, which is shared between all of the currently supported boards, and do it such that only a very minimal amount of changes are needed to each board - the only required change was done in mt8183-pumpkin, using a phandle to assign the display to DPI0. All boards featuring any display functionality will extend this common graph to hook the display controller of the SoC to their specific output port(s). Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250724083914.61351-33-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt8183-pumpkin.dts | 8 +- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 239 +++++++++++++++++- 2 files changed, 238 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 8d88cb861a5ad..f60ef3e53a09b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -531,10 +531,8 @@ pinctrl-0 = <&dpi_func_pins>; pinctrl-1 = <&dpi_idle_pins>; status = "okay"; +}; - port { - dpi_out: endpoint { - remote-endpoint = <&it66121_in>; - }; - }; +&dpi_out { + remote-endpoint = <&it66121_in>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 3c1fe80e64b9c..960d8955d018c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1667,6 +1667,21 @@ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + + mmsys_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&ovl_2l1_in>; + }; + }; }; dma-controller0@14001000 { @@ -1733,6 +1748,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_ep_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&ovl_2l0_in>; + }; + }; + }; }; ovl_2l0: ovl@14009000 { @@ -1743,6 +1777,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; ovl_2l1: ovl@1400a000 { @@ -1753,6 +1806,25 @@ clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l1_in: endpoint { + remote-endpoint = <&mmsys_ep_ext>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l1_out: endpoint { + remote-endpoint = <&rdma1_in>; + }; + }; + }; }; rdma0: rdma@1400b000 { @@ -1764,6 +1836,25 @@ iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl_2l0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; rdma1: rdma@1400c000 { @@ -1775,6 +1866,25 @@ iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&ovl_2l1_out>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { + remote-endpoint = <&dpi_in>; + }; + }; + }; }; color0: color@1400e000 { @@ -1785,6 +1895,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1400f000 { @@ -1794,6 +1923,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@14010000 { @@ -1803,6 +1951,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@14011000 { @@ -1812,6 +1979,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@14012000 { @@ -1821,6 +2007,25 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; }; dsi0: dsi@14014000 { @@ -1837,8 +2042,21 @@ phy-names = "dphy"; status = "disabled"; - port { - dsi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { }; + }; }; }; @@ -1853,8 +2071,21 @@ clock-names = "pixel", "engine", "pll"; status = "disabled"; - port { - dpi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi_in: endpoint { + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + reg = <1>; + dpi_out: endpoint { }; + }; }; }; -- 2.47.3