From e7ee01debe8eab87b8ec9020df9ccf60817e15ab Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 25 Apr 2013 13:37:00 +0200 Subject: [PATCH] i2c: Clean coding style violations Synchronization with mainline. Signed-off-by: Michal Simek --- drivers/i2c/zynq_i2c.c | 75 +++++++++++++++++++++++------------------- 1 file changed, 41 insertions(+), 34 deletions(-) diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index 14ca1634717..4bd24ccbbcd 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -1,10 +1,12 @@ /* - * Driver for the Zynq-7000 PSS I2C controller + * Driver for the Zynq-7000 PS I2C controller * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) * * Author: Joe Hershberger * Copyright (c) 2012 Joe Hershberger. * + * Copyright (c) 2012-2013 Xilinx, Michal Simek + * * See file CREDITS for list of people who contributed to this * project. * @@ -45,34 +47,34 @@ struct zynq_i2c_registers { }; /* Control register fields */ -#define ZYNQ_I2C_CONTROL_RW 0x00000001 -#define ZYNQ_I2C_CONTROL_MS 0x00000002 -#define ZYNQ_I2C_CONTROL_NEA 0x00000004 -#define ZYNQ_I2C_CONTROL_ACKEN 0x00000008 -#define ZYNQ_I2C_CONTROL_HOLD 0x00000010 -#define ZYNQ_I2C_CONTROL_SLVMON 0x00000020 -#define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040 -#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8 -#define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00 -#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14 -#define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000 +#define ZYNQ_I2C_CONTROL_RW 0x00000001 +#define ZYNQ_I2C_CONTROL_MS 0x00000002 +#define ZYNQ_I2C_CONTROL_NEA 0x00000004 +#define ZYNQ_I2C_CONTROL_ACKEN 0x00000008 +#define ZYNQ_I2C_CONTROL_HOLD 0x00000010 +#define ZYNQ_I2C_CONTROL_SLVMON 0x00000020 +#define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040 +#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8 +#define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00 +#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14 +#define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000 /* Status register values */ -#define ZYNQ_I2C_STATUS_RXDV 0x00000020 -#define ZYNQ_I2C_STATUS_TXDV 0x00000040 -#define ZYNQ_I2C_STATUS_RXOVF 0x00000080 -#define ZYNQ_I2C_STATUS_BA 0x00000100 +#define ZYNQ_I2C_STATUS_RXDV 0x00000020 +#define ZYNQ_I2C_STATUS_TXDV 0x00000040 +#define ZYNQ_I2C_STATUS_RXOVF 0x00000080 +#define ZYNQ_I2C_STATUS_BA 0x00000100 /* Interrupt register fields */ -#define ZYNQ_I2C_INTERRUPT_COMP 0x00000001 -#define ZYNQ_I2C_INTERRUPT_DATA 0x00000002 -#define ZYNQ_I2C_INTERRUPT_NACK 0x00000004 -#define ZYNQ_I2C_INTERRUPT_TO 0x00000008 -#define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010 -#define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020 -#define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040 -#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080 -#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200 +#define ZYNQ_I2C_INTERRUPT_COMP 0x00000001 +#define ZYNQ_I2C_INTERRUPT_DATA 0x00000002 +#define ZYNQ_I2C_INTERRUPT_NACK 0x00000004 +#define ZYNQ_I2C_INTERRUPT_TO 0x00000008 +#define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010 +#define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020 +#define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040 +#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080 +#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200 #if defined(CONFIG_ZYNQ_I2C_CTLR_0) #define ZYNQ_I2C_BASE 0xE0004000 @@ -89,7 +91,7 @@ struct zynq_i2c_registers { #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ static struct zynq_i2c_registers *zynq_i2c = - (struct zynq_i2c_registers *) ZYNQ_I2C_BASE; + (struct zynq_i2c_registers *)ZYNQ_I2C_BASE; /* I2C init called by cmd_i2c when doing 'i2c reset'. */ void i2c_init(int requested_speed, int slaveadd) @@ -109,6 +111,7 @@ static void zynq_i2c_debug_status(void) int int_status; int status; int_status = readl(&zynq_i2c->interrupt_status); + status = readl(&zynq_i2c->status); if (int_status || status) { debug("Status: "); @@ -148,6 +151,7 @@ static void zynq_i2c_debug_status(void) static u32 zynq_i2c_wait(u32 mask) { int timeout, int_status; + for (timeout = 0; timeout < 100; timeout++) { udelay(100); int_status = readl(&zynq_i2c->interrupt_status); @@ -159,6 +163,7 @@ static u32 zynq_i2c_wait(u32 mask) #endif /* Clear interrupt status flags */ writel(int_status & mask, &zynq_i2c->interrupt_status); + return int_status & mask; } @@ -191,15 +196,17 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) u32 i = 0; u8 *cur_data = data; - /* check the hardware can handle the requested bytes */ + /* Check the hardware can handle the requested bytes */ if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) return -EINVAL; /* Write the register address */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_HOLD); - /* Temporarily disable restart (by clearing hold)... */ - /* It doesn't seem to work. */ + /* + * Temporarily disable restart (by clearing hold) + * It doesn't seem to work. + */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW | ZYNQ_I2C_CONTROL_HOLD); writel(0xFF, &zynq_i2c->interrupt_status); @@ -207,7 +214,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) writel(addr >> (8*alen), &zynq_i2c->data); writel(dev, &zynq_i2c->address); - /* wait for the address to be sent */ + /* Wait for the address to be sent */ if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); @@ -221,7 +228,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) writel(dev, &zynq_i2c->address); writel(length, &zynq_i2c->transfer_size); - /* wait for data */ + /* Wait for data */ do { status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | ZYNQ_I2C_INTERRUPT_DATA); @@ -231,7 +238,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) return -ETIMEDOUT; } debug("Read %d bytes\n", - length - readl(&zynq_i2c->transfer_size)); + length - readl(&zynq_i2c->transfer_size)); for (; i < length - readl(&zynq_i2c->transfer_size); i++) *(cur_data++) = readl(&zynq_i2c->data); } while (readl(&zynq_i2c->transfer_size) != 0); @@ -274,7 +281,7 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, - ZYNQ_I2C_CONTROL_HOLD); + ZYNQ_I2C_CONTROL_HOLD); return -ETIMEDOUT; } } @@ -282,7 +289,7 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) /* All done... release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - /* wait for the address and data to be sent */ + /* Wait for the address and data to be sent */ if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) return -ETIMEDOUT; return 0; -- 2.47.3