From e85fc2c62321201222d3e30191f376760978ccca Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 8 Oct 2025 14:55:54 -0700 Subject: [PATCH] target/arm: Implement GCSSS2 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20251008215613.300150-55-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs-gcs.c | 3 +++ target/arm/cpregs.h | 1 + target/arm/tcg/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index eda5c498d7..1ed52a211a 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -132,6 +132,9 @@ static const ARMCPRegInfo gcs_reginfo[] = { { .name = "GCSSS1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 7, .opc2 = 2, .access = PL0_W, .type = ARM_CP_GCSSS1 }, + { .name = "GCSSS2", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 7, .opc2 = 3, + .access = PL0_R, .type = ARM_CP_GCSSS2 }, { .name = "GCSPUSHX", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 7, .opc2 = 4, .access = PL1_W, .accessfn = access_gcspushx, .fgt = FGT_NGCSEPP, diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index e7e7050880..732c07506d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -54,6 +54,7 @@ enum { ARM_CP_GCSPOPX = 0x000b, ARM_CP_GCSPOPCX = 0x000c, ARM_CP_GCSSS1 = 0x000d, + ARM_CP_GCSSS2 = 0x000e, /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST = 1 << 4, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 82ddf4e1dc..d58257be40 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2668,6 +2668,35 @@ static void gen_gcsss1(DisasContext *s, int rt) tcg_gen_andi_i64(gcspr, inptr, ~7); } +static void gen_gcsss2(DisasContext *s, int rt) +{ + TCGv_i64 gcspr = cpu_gcspr[s->current_el]; + int mmuidx = core_gcs_mem_index(s->mmu_idx); + MemOp mop = finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 outptr = tcg_temp_new_i64(); + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGLabel *fail_label = + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSSS2, rt)); + + /* Validate that the new stack has an in-progress cap. */ + tcg_gen_qemu_ld_i64(outptr, gcspr, mmuidx, mop); + tcg_gen_andi_i64(tmp, outptr, 7); + tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 5, fail_label); + + /* Push a valid cap to the old stack. */ + tcg_gen_andi_i64(outptr, outptr, ~7); + tcg_gen_addi_i64(outptr, outptr, -8); + tcg_gen_deposit_i64(tmp, outptr, tcg_constant_i64(1), 0, 12); + tcg_gen_qemu_st_i64(tmp, outptr, mmuidx, mop); + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + + /* Pop the in-progress cap from the new stack. */ + tcg_gen_addi_i64(gcspr, gcspr, 8); + + /* Return a pointer to the old stack cap. */ + tcg_gen_mov_i64(cpu_reg(s, rt), outptr); +} + /* * Look up @key, returning the cpreg, which must exist. * Additionally, the new cpreg must also be accessible. @@ -3014,6 +3043,11 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcsss1(s, rt); } return; + case ARM_CP_GCSSS2: + if (s->gcs_en) { + gen_gcsss2(s, rt); + } + return; default: g_assert_not_reached(); } -- 2.47.3