From ebab5a46e7172c63d3fc8d41073b5d3f64d90e81 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 4 Jun 2014 20:06:54 -0700 Subject: [PATCH] 3.4-stable patches added patches: drm-fix-documentation-for-drm_crtc_set_mode.patch drm-i915-close-race-between-processing-unpin-task-and-queueing-the-flip.patch drm-i915-sdvo-clean-up-connectors-on-intel_sdvo_init-failures.patch drm-nouveau-fix-init-with-agpgart-uninorth.patch drm-radeon-add-connector-table-for-mac-g4-silver.patch drm-radeon-add-connector-table-for-sam440ep-embedded-board.patch drm-radeon-dce32-use-fractional-fb-dividers-for-high-clocks.patch drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch drm-radeon-fix-typo-in-evergreen_mc_resume.patch --- ...-documentation-for-drm_crtc_set_mode.patch | 34 ++++ ...ing-unpin-task-and-queueing-the-flip.patch | 189 ++++++++++++++++++ ...nnectors-on-intel_sdvo_init-failures.patch | 86 ++++++++ ...uveau-fix-init-with-agpgart-uninorth.patch | 44 ++++ ...dd-connector-table-for-mac-g4-silver.patch | 106 ++++++++++ ...or-table-for-sam440ep-embedded-board.patch | 115 +++++++++++ ...actional-fb-dividers-for-high-clocks.patch | 32 +++ ...ix-amd-afusion-gpu-setup-aka-sumo-v2.patch | 49 +++++ ...deon-fix-typo-in-evergreen_mc_resume.patch | 39 ++++ queue-3.4/series | 9 + 10 files changed, 703 insertions(+) create mode 100644 queue-3.4/drm-fix-documentation-for-drm_crtc_set_mode.patch create mode 100644 queue-3.4/drm-i915-close-race-between-processing-unpin-task-and-queueing-the-flip.patch create mode 100644 queue-3.4/drm-i915-sdvo-clean-up-connectors-on-intel_sdvo_init-failures.patch create mode 100644 queue-3.4/drm-nouveau-fix-init-with-agpgart-uninorth.patch create mode 100644 queue-3.4/drm-radeon-add-connector-table-for-mac-g4-silver.patch create mode 100644 queue-3.4/drm-radeon-add-connector-table-for-sam440ep-embedded-board.patch create mode 100644 queue-3.4/drm-radeon-dce32-use-fractional-fb-dividers-for-high-clocks.patch create mode 100644 queue-3.4/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch create mode 100644 queue-3.4/drm-radeon-fix-typo-in-evergreen_mc_resume.patch diff --git a/queue-3.4/drm-fix-documentation-for-drm_crtc_set_mode.patch b/queue-3.4/drm-fix-documentation-for-drm_crtc_set_mode.patch new file mode 100644 index 00000000000..52ce4e8d8c8 --- /dev/null +++ b/queue-3.4/drm-fix-documentation-for-drm_crtc_set_mode.patch @@ -0,0 +1,34 @@ +From 56bd27c70e51a909f768f6bb62e93ad78e5c87e2 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 9 Nov 2012 17:26:32 +0000 +Subject: drm: fix documentation for drm_crtc_set_mode() + +From: Alex Deucher + +commit 4c9287c6009b37754c42e0ba73a4cc79de92d8f8 upstream. + +x and y parameters are offsets, not width/height + +Signed-off-by: Alex Deucher +Signed-off-by: Dave Airlie +Signed-off-by: Ben Hutchings +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_crtc_helper.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/drm_crtc_helper.c ++++ b/drivers/gpu/drm/drm_crtc_helper.c +@@ -328,8 +328,8 @@ drm_crtc_prepare_encoders(struct drm_dev + * drm_crtc_set_mode - set a mode + * @crtc: CRTC to program + * @mode: mode to use +- * @x: width of mode +- * @y: height of mode ++ * @x: horizontal offset into the surface ++ * @y: vertical offset into the surface + * + * LOCKING: + * Caller must hold mode config lock. diff --git a/queue-3.4/drm-i915-close-race-between-processing-unpin-task-and-queueing-the-flip.patch b/queue-3.4/drm-i915-close-race-between-processing-unpin-task-and-queueing-the-flip.patch new file mode 100644 index 00000000000..e284f12d242 --- /dev/null +++ b/queue-3.4/drm-i915-close-race-between-processing-unpin-task-and-queueing-the-flip.patch @@ -0,0 +1,189 @@ +From e7d841ca03b7ab668620045cd7b428eda9f41601 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Mon, 3 Dec 2012 11:36:30 +0000 +Subject: drm/i915: Close race between processing unpin task and queueing the flip + +From: Chris Wilson + +commit e7d841ca03b7ab668620045cd7b428eda9f41601 upstream. + +Before queuing the flip but crucially after attaching the unpin-work to +the crtc, we continue to setup the unpin-work. However, should the +hardware fire early, we see the connected unpin-work and queue the task. +The task then promptly runs and unpins the fb before we finish taking +the required references or even pinning it... Havoc. + +To close the race, we use the flip-pending atomic to indicate when the +flip is finally setup and enqueued. So during the flip-done processing, +we can check more accurately whether the flip was expected. + +v2: Add the appropriate mb() to ensure that the writes to the page-flip +worker are complete prior to marking it active and emitting the MI_FLIP. +On the read side, the mb should be enforced by the spinlocks. + +Signed-off-by: Chris Wilson +Cc: stable@vger.kernel.org +[danvet: Review the barriers a bit, we need a write barrier both +before and after updating ->pending. Similarly we need a read barrier +in the interrupt handler both before and after reading ->pending. With +well-ordered irqs only one barrier in each place should be required, +but since this patch explicitly sets out to combat spurious interrupts +with is staged activation of the unpin work we need to go full-bore on +the barriers, too. Discussed with Chris Wilson on irc and changes +acked by him.] +Signed-off-by: Daniel Vetter +[wml: Backported to 3.4: adjust context] +Signed-off-by: Weng Meiling +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/i915_debugfs.c | 4 +-- + drivers/gpu/drm/i915/i915_irq.c | 4 ++- + drivers/gpu/drm/i915/intel_display.c | 39 ++++++++++++++++++++++++++++------- + drivers/gpu/drm/i915/intel_drv.h | 5 +++- + 4 files changed, 41 insertions(+), 11 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_debugfs.c ++++ b/drivers/gpu/drm/i915/i915_debugfs.c +@@ -340,7 +340,7 @@ static int i915_gem_pageflip_info(struct + seq_printf(m, "No flip due on pipe %c (plane %c)\n", + pipe, plane); + } else { +- if (!work->pending) { ++ if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { + seq_printf(m, "Flip queued on pipe %c (plane %c)\n", + pipe, plane); + } else { +@@ -351,7 +351,7 @@ static int i915_gem_pageflip_info(struct + seq_printf(m, "Stall check enabled, "); + else + seq_printf(m, "Stall check waiting for page flip ioctl, "); +- seq_printf(m, "%d prepares\n", work->pending); ++ seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); + + if (work->old_fb_obj) { + struct drm_i915_gem_object *obj = work->old_fb_obj; +--- a/drivers/gpu/drm/i915/i915_irq.c ++++ b/drivers/gpu/drm/i915/i915_irq.c +@@ -1251,7 +1251,9 @@ static void i915_pageflip_stall_check(st + spin_lock_irqsave(&dev->event_lock, flags); + work = intel_crtc->unpin_work; + +- if (work == NULL || work->pending || !work->enable_stall_check) { ++ if (work == NULL || ++ atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || ++ !work->enable_stall_check) { + /* Either the pending flip IRQ arrived, or we're too early. Don't check */ + spin_unlock_irqrestore(&dev->event_lock, flags); + return; +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -7245,11 +7245,18 @@ static void do_intel_finish_page_flip(st + + spin_lock_irqsave(&dev->event_lock, flags); + work = intel_crtc->unpin_work; +- if (work == NULL || !work->pending) { ++ ++ /* Ensure we don't miss a work->pending update ... */ ++ smp_rmb(); ++ ++ if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { + spin_unlock_irqrestore(&dev->event_lock, flags); + return; + } + ++ /* and that the unpin work is consistent wrt ->pending. */ ++ smp_rmb(); ++ + intel_crtc->unpin_work = NULL; + + if (work->event) { +@@ -7321,16 +7328,25 @@ void intel_prepare_page_flip(struct drm_ + to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); + unsigned long flags; + ++ /* NB: An MMIO update of the plane base pointer will also ++ * generate a page-flip completion irq, i.e. every modeset ++ * is also accompanied by a spurious intel_prepare_page_flip(). ++ */ + spin_lock_irqsave(&dev->event_lock, flags); +- if (intel_crtc->unpin_work) { +- if ((++intel_crtc->unpin_work->pending) > 1) +- DRM_ERROR("Prepared flip multiple times\n"); +- } else { +- DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); +- } ++ if (intel_crtc->unpin_work) ++ atomic_inc_not_zero(&intel_crtc->unpin_work->pending); + spin_unlock_irqrestore(&dev->event_lock, flags); + } + ++inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) ++{ ++ /* Ensure that the work item is consistent when activating it ... */ ++ smp_wmb(); ++ atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); ++ /* and that it is marked active as soon as the irq could fire. */ ++ smp_wmb(); ++} ++ + static int intel_gen2_queue_flip(struct drm_device *dev, + struct drm_crtc *crtc, + struct drm_framebuffer *fb, +@@ -7367,6 +7383,8 @@ static int intel_gen2_queue_flip(struct + OUT_RING(fb->pitches[0]); + OUT_RING(obj->gtt_offset + offset); + OUT_RING(0); /* aux display base address, unused */ ++ ++ intel_mark_page_flip_active(intel_crtc); + ADVANCE_LP_RING(); + return 0; + +@@ -7410,6 +7428,7 @@ static int intel_gen3_queue_flip(struct + OUT_RING(obj->gtt_offset + offset); + OUT_RING(MI_NOOP); + ++ intel_mark_page_flip_active(intel_crtc); + ADVANCE_LP_RING(); + return 0; + +@@ -7453,6 +7472,8 @@ static int intel_gen4_queue_flip(struct + pf = 0; + pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; + OUT_RING(pf | pipesrc); ++ ++ intel_mark_page_flip_active(intel_crtc); + ADVANCE_LP_RING(); + return 0; + +@@ -7494,6 +7515,8 @@ static int intel_gen6_queue_flip(struct + pf = 0; + pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; + OUT_RING(pf | pipesrc); ++ ++ intel_mark_page_flip_active(intel_crtc); + ADVANCE_LP_RING(); + return 0; + +@@ -7548,6 +7571,8 @@ static int intel_gen7_queue_flip(struct + intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); + intel_ring_emit(ring, (obj->gtt_offset)); + intel_ring_emit(ring, (MI_NOOP)); ++ ++ intel_mark_page_flip_active(intel_crtc); + intel_ring_advance(ring); + return 0; + +--- a/drivers/gpu/drm/i915/intel_drv.h ++++ b/drivers/gpu/drm/i915/intel_drv.h +@@ -277,7 +277,10 @@ struct intel_unpin_work { + struct drm_i915_gem_object *old_fb_obj; + struct drm_i915_gem_object *pending_flip_obj; + struct drm_pending_vblank_event *event; +- int pending; ++ atomic_t pending; ++#define INTEL_FLIP_INACTIVE 0 ++#define INTEL_FLIP_PENDING 1 ++#define INTEL_FLIP_COMPLETE 2 + bool enable_stall_check; + }; + diff --git a/queue-3.4/drm-i915-sdvo-clean-up-connectors-on-intel_sdvo_init-failures.patch b/queue-3.4/drm-i915-sdvo-clean-up-connectors-on-intel_sdvo_init-failures.patch new file mode 100644 index 00000000000..93d4115bf21 --- /dev/null +++ b/queue-3.4/drm-i915-sdvo-clean-up-connectors-on-intel_sdvo_init-failures.patch @@ -0,0 +1,86 @@ +From 8a3a3f4a507d46b1c22c923733b172eebcf188f1 Mon Sep 17 00:00:00 2001 +From: Jani Nikula +Date: Mon, 12 Nov 2012 18:31:35 +0200 +Subject: drm/i915/sdvo: clean up connectors on intel_sdvo_init() failures + +From: Jani Nikula + +commit d0ddfbd3d1346c1f481ec2289eef350cdba64b42 upstream. + +Any failures in intel_sdvo_init() after the intel_sdvo_setup_output() call +left behind ghost connectors, attached (with a dangling pointer) to the +sdvo that has been cleaned up and freed. Properly destroy any connectors +attached to the encoder. + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=46381 +CC: Chris Wilson +Signed-off-by: Jani Nikula +Tested-by: bjo@nord-west.org +[danvet: added a comment to explain why we need to clean up connectors +even when sdvo_output_setup fails.] +Signed-off-by: Daniel Vetter +[bwh: Backported to 3.2: adjust context] +Signed-off-by: Ben Hutchings +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_sdvo.c | 22 +++++++++++++++++++--- + 1 file changed, 19 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_sdvo.c ++++ b/drivers/gpu/drm/i915/intel_sdvo.c +@@ -2265,6 +2265,18 @@ intel_sdvo_output_setup(struct intel_sdv + return true; + } + ++static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) ++{ ++ struct drm_device *dev = intel_sdvo->base.base.dev; ++ struct drm_connector *connector, *tmp; ++ ++ list_for_each_entry_safe(connector, tmp, ++ &dev->mode_config.connector_list, head) { ++ if (intel_attached_encoder(connector) == &intel_sdvo->base) ++ intel_sdvo_destroy(connector); ++ } ++} ++ + static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, + struct intel_sdvo_connector *intel_sdvo_connector, + int type) +@@ -2583,7 +2595,8 @@ bool intel_sdvo_init(struct drm_device * + intel_sdvo->caps.output_flags) != true) { + DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", + IS_SDVOB(sdvo_reg) ? 'B' : 'C'); +- goto err; ++ /* Output_setup can leave behind connectors! */ ++ goto err_output; + } + + /* Only enable the hotplug irq if we need it, to work around noisy +@@ -2596,12 +2609,12 @@ bool intel_sdvo_init(struct drm_device * + + /* Set the input timing to the screen. Assume always input 0. */ + if (!intel_sdvo_set_target_input(intel_sdvo)) +- goto err; ++ goto err_output; + + if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, + &intel_sdvo->pixel_clock_min, + &intel_sdvo->pixel_clock_max)) +- goto err; ++ goto err_output; + + DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " + "clock range %dMHz - %dMHz, " +@@ -2621,6 +2634,9 @@ bool intel_sdvo_init(struct drm_device * + (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); + return true; + ++err_output: ++ intel_sdvo_output_cleanup(intel_sdvo); ++ + err: + drm_encoder_cleanup(&intel_encoder->base); + i2c_del_adapter(&intel_sdvo->ddc); diff --git a/queue-3.4/drm-nouveau-fix-init-with-agpgart-uninorth.patch b/queue-3.4/drm-nouveau-fix-init-with-agpgart-uninorth.patch new file mode 100644 index 00000000000..caf7069efdd --- /dev/null +++ b/queue-3.4/drm-nouveau-fix-init-with-agpgart-uninorth.patch @@ -0,0 +1,44 @@ +From 55fa88bba3378e444ab8c2fe21f6f7e0046355a8 Mon Sep 17 00:00:00 2001 +From: Aaro Koskinen +Date: Mon, 31 Dec 2012 03:34:59 +0200 +Subject: drm/nouveau: fix init with agpgart-uninorth +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Aaro Koskinen + +commit eda85d6ad490923152544fba0473798b6cc0edf6 upstream. + +Check that the AGP aperture can be mapped. This follows a similar change +done for Radeon (commit 365048ff, drm/radeon: AGP memory is only I/O if +the aperture can be mapped by the CPU.). + +The patch fixes the following error seen on G5 iMac: + + nouveau E[ DRM] failed to create kernel channel, -12 + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58806 +Reviewed-by: Michel Dänzer +Signed-off-by: Aaro Koskinen +Signed-off-by: Dave Airlie +[bwh: Backported to 3.2: adjust context] +Signed-off-by: Ben Hutchings +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/nouveau/nouveau_bo.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/nouveau/nouveau_bo.c ++++ b/drivers/gpu/drm/nouveau/nouveau_bo.c +@@ -946,7 +946,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo + if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { + mem->bus.offset = mem->start << PAGE_SHIFT; + mem->bus.base = dev_priv->gart_info.aper_base; +- mem->bus.is_iomem = true; ++ mem->bus.is_iomem = !dev->agp->cant_use_aperture; + } + #endif + break; diff --git a/queue-3.4/drm-radeon-add-connector-table-for-mac-g4-silver.patch b/queue-3.4/drm-radeon-add-connector-table-for-mac-g4-silver.patch new file mode 100644 index 00000000000..717873fa2c0 --- /dev/null +++ b/queue-3.4/drm-radeon-add-connector-table-for-mac-g4-silver.patch @@ -0,0 +1,106 @@ +From 8b003924dec64459a562af80f60a3b67789dc856 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 20 Dec 2012 16:35:47 -0500 +Subject: drm/radeon: add connector table for Mac G4 Silver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit cafa59b9011a7790be4ddd5979419259844a165d upstream. + +Apple cards do not provide data tables in the vbios +so we have to hard code the connector parameters +in the driver. + +Reported-by: Albrecht Dreß +Signed-off-by: Alex Deucher +Signed-off-by: Ben Hutchings +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_combios.c | 51 ++++++++++++++++++++++++++++++++ + drivers/gpu/drm/radeon/radeon_mode.h | 3 + + 2 files changed, 53 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/radeon/radeon_combios.c ++++ b/drivers/gpu/drm/radeon/radeon_combios.c +@@ -1484,6 +1484,9 @@ bool radeon_get_legacy_connector_info_fr + of_machine_is_compatible("PowerBook6,7")) { + /* ibook */ + rdev->mode_info.connector_table = CT_IBOOK; ++ } else if (of_machine_is_compatible("PowerMac3,5")) { ++ /* PowerMac G4 Silver radeon 7500 */ ++ rdev->mode_info.connector_table = CT_MAC_G4_SILVER; + } else if (of_machine_is_compatible("PowerMac4,4")) { + /* emac */ + rdev->mode_info.connector_table = CT_EMAC; +@@ -2146,6 +2149,54 @@ bool radeon_get_legacy_connector_info_fr + DRM_MODE_CONNECTOR_SVIDEO, + &ddc_i2c, + CONNECTOR_OBJECT_ID_SVIDEO, ++ &hpd); ++ break; ++ case CT_MAC_G4_SILVER: ++ DRM_INFO("Connector Table: %d (mac g4 silver)\n", ++ rdev->mode_info.connector_table); ++ /* DVI-I - tv dac, int tmds */ ++ ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); ++ hpd.hpd = RADEON_HPD_1; /* ??? */ ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_DFP1_SUPPORT, ++ 0), ++ ATOM_DEVICE_DFP1_SUPPORT); ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_CRT2_SUPPORT, ++ 2), ++ ATOM_DEVICE_CRT2_SUPPORT); ++ radeon_add_legacy_connector(dev, 0, ++ ATOM_DEVICE_DFP1_SUPPORT | ++ ATOM_DEVICE_CRT2_SUPPORT, ++ DRM_MODE_CONNECTOR_DVII, &ddc_i2c, ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, ++ &hpd); ++ /* VGA - primary dac */ ++ ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); ++ hpd.hpd = RADEON_HPD_NONE; ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_CRT1_SUPPORT, ++ 1), ++ ATOM_DEVICE_CRT1_SUPPORT); ++ radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, ++ DRM_MODE_CONNECTOR_VGA, &ddc_i2c, ++ CONNECTOR_OBJECT_ID_VGA, ++ &hpd); ++ /* TV - TV DAC */ ++ ddc_i2c.valid = false; ++ hpd.hpd = RADEON_HPD_NONE; ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_TV1_SUPPORT, ++ 2), ++ ATOM_DEVICE_TV1_SUPPORT); ++ radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, ++ DRM_MODE_CONNECTOR_SVIDEO, ++ &ddc_i2c, ++ CONNECTOR_OBJECT_ID_SVIDEO, + &hpd); + break; + default: +--- a/drivers/gpu/drm/radeon/radeon_mode.h ++++ b/drivers/gpu/drm/radeon/radeon_mode.h +@@ -210,7 +210,8 @@ enum radeon_connector_table { + CT_RN50_POWER, + CT_MAC_X800, + CT_MAC_G5_9600, +- CT_SAM440EP ++ CT_SAM440EP, ++ CT_MAC_G4_SILVER + }; + + enum radeon_dvo_chip { diff --git a/queue-3.4/drm-radeon-add-connector-table-for-sam440ep-embedded-board.patch b/queue-3.4/drm-radeon-add-connector-table-for-sam440ep-embedded-board.patch new file mode 100644 index 00000000000..4a5f4272887 --- /dev/null +++ b/queue-3.4/drm-radeon-add-connector-table-for-sam440ep-embedded-board.patch @@ -0,0 +1,115 @@ +From c63d1a742f2ef1fb6878e69f7314c30157e031f2 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 2 May 2012 12:10:21 -0400 +Subject: drm/radeon: add connector table for SAM440ep embedded board + +From: Alex Deucher + +commit 6a556039e7823d27a0a7f7724d4d455053ea9253 upstream. + +RV250 found on ppc embedded boards. + +Cc: Hans Verkuil +Signed-off-by: Alex Deucher +Signed-off-by: Dave Airlie +Signed-off-by: Ben Hutchings +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_combios.c | 66 ++++++++++++++++++++++++++++++++ + drivers/gpu/drm/radeon/radeon_mode.h | 1 + 2 files changed, 67 insertions(+) + +--- a/drivers/gpu/drm/radeon/radeon_combios.c ++++ b/drivers/gpu/drm/radeon/radeon_combios.c +@@ -1509,6 +1509,11 @@ bool radeon_get_legacy_connector_info_fr + (rdev->pdev->subsystem_device == 0x4150)) { + /* Mac G5 tower 9600 */ + rdev->mode_info.connector_table = CT_MAC_G5_9600; ++ } else if ((rdev->pdev->device == 0x4c66) && ++ (rdev->pdev->subsystem_vendor == 0x1002) && ++ (rdev->pdev->subsystem_device == 0x4c66)) { ++ /* SAM440ep RV250 embedded board */ ++ rdev->mode_info.connector_table = CT_SAM440EP; + } else + #endif /* CONFIG_PPC_PMAC */ + #ifdef CONFIG_PPC64 +@@ -2080,6 +2085,67 @@ bool radeon_get_legacy_connector_info_fr + DRM_MODE_CONNECTOR_SVIDEO, + &ddc_i2c, + CONNECTOR_OBJECT_ID_SVIDEO, ++ &hpd); ++ break; ++ case CT_SAM440EP: ++ DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", ++ rdev->mode_info.connector_table); ++ /* LVDS */ ++ ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); ++ hpd.hpd = RADEON_HPD_NONE; ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_LCD1_SUPPORT, ++ 0), ++ ATOM_DEVICE_LCD1_SUPPORT); ++ radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, ++ DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, ++ CONNECTOR_OBJECT_ID_LVDS, ++ &hpd); ++ /* DVI-I - secondary dac, int tmds */ ++ ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); ++ hpd.hpd = RADEON_HPD_1; /* ??? */ ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_DFP1_SUPPORT, ++ 0), ++ ATOM_DEVICE_DFP1_SUPPORT); ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_CRT2_SUPPORT, ++ 2), ++ ATOM_DEVICE_CRT2_SUPPORT); ++ radeon_add_legacy_connector(dev, 1, ++ ATOM_DEVICE_DFP1_SUPPORT | ++ ATOM_DEVICE_CRT2_SUPPORT, ++ DRM_MODE_CONNECTOR_DVII, &ddc_i2c, ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, ++ &hpd); ++ /* VGA - primary dac */ ++ ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); ++ hpd.hpd = RADEON_HPD_NONE; ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_CRT1_SUPPORT, ++ 1), ++ ATOM_DEVICE_CRT1_SUPPORT); ++ radeon_add_legacy_connector(dev, 2, ++ ATOM_DEVICE_CRT1_SUPPORT, ++ DRM_MODE_CONNECTOR_VGA, &ddc_i2c, ++ CONNECTOR_OBJECT_ID_VGA, ++ &hpd); ++ /* TV - TV DAC */ ++ ddc_i2c.valid = false; ++ hpd.hpd = RADEON_HPD_NONE; ++ radeon_add_legacy_encoder(dev, ++ radeon_get_encoder_enum(dev, ++ ATOM_DEVICE_TV1_SUPPORT, ++ 2), ++ ATOM_DEVICE_TV1_SUPPORT); ++ radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, ++ DRM_MODE_CONNECTOR_SVIDEO, ++ &ddc_i2c, ++ CONNECTOR_OBJECT_ID_SVIDEO, + &hpd); + break; + default: +--- a/drivers/gpu/drm/radeon/radeon_mode.h ++++ b/drivers/gpu/drm/radeon/radeon_mode.h +@@ -210,6 +210,7 @@ enum radeon_connector_table { + CT_RN50_POWER, + CT_MAC_X800, + CT_MAC_G5_9600, ++ CT_SAM440EP + }; + + enum radeon_dvo_chip { diff --git a/queue-3.4/drm-radeon-dce32-use-fractional-fb-dividers-for-high-clocks.patch b/queue-3.4/drm-radeon-dce32-use-fractional-fb-dividers-for-high-clocks.patch new file mode 100644 index 00000000000..bfbb6dc1a9b --- /dev/null +++ b/queue-3.4/drm-radeon-dce32-use-fractional-fb-dividers-for-high-clocks.patch @@ -0,0 +1,32 @@ +From a0d3e01dadd633961769f2c388599b0b6f08c1df Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 13 Nov 2012 18:03:41 -0500 +Subject: drm/radeon/dce32+: use fractional fb dividers for high clocks + +From: Alex Deucher + +commit a02dc74b317d78298cb0587b9b1f6f741fd5c139 upstream. + +Fixes flickering with some high res montiors. + +Signed-off-by: Alex Deucher +[bwh: Backported to 3.2: use pll->flags instead of radeon_crtc->pll_flags] +Signed-off-by: Ben Hutchings +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/atombios_crtc.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -573,6 +573,8 @@ static u32 atombios_adjust_pll(struct dr + /* use frac fb div on APUs */ + if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) + pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; ++ if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) ++ pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; + } else { + pll->flags |= RADEON_PLL_LEGACY; + diff --git a/queue-3.4/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch b/queue-3.4/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch new file mode 100644 index 00000000000..afb05bddbc0 --- /dev/null +++ b/queue-3.4/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch @@ -0,0 +1,49 @@ +From 61252278ee286b891e23dc0009aed1a9da1f0b0e Mon Sep 17 00:00:00 2001 +From: Jerome Glisse +Date: Tue, 11 Dec 2012 11:56:52 -0500 +Subject: drm/radeon: fix amd afusion gpu setup aka sumo v2 + +From: Jerome Glisse + +commit bd25f0783dc3fb72e1e2779c2b99b2d34b67fa8a upstream. + +Set the proper number of tile pipe that should be a multiple of +pipe depending on the number of se engine. + +Fix: +https://bugs.freedesktop.org/show_bug.cgi?id=56405 +https://bugs.freedesktop.org/show_bug.cgi?id=56720 + +v2: Don't change sumo2 + +Signed-off-by: Jerome Glisse +Reviewed-by: Alex Deucher +[bwh: Backported to 3.2: don't define/use *_GB_ADDR_CONFIG_GOLDEN] +Signed-off-by: Ben Hutchings +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -1874,7 +1874,7 @@ static void evergreen_gpu_init(struct ra + case CHIP_SUMO: + rdev->config.evergreen.num_ses = 1; + rdev->config.evergreen.max_pipes = 4; +- rdev->config.evergreen.max_tile_pipes = 2; ++ rdev->config.evergreen.max_tile_pipes = 4; + if (rdev->pdev->device == 0x9648) + rdev->config.evergreen.max_simds = 3; + else if ((rdev->pdev->device == 0x9647) || +@@ -1963,7 +1963,7 @@ static void evergreen_gpu_init(struct ra + break; + case CHIP_CAICOS: + rdev->config.evergreen.num_ses = 1; +- rdev->config.evergreen.max_pipes = 4; ++ rdev->config.evergreen.max_pipes = 2; + rdev->config.evergreen.max_tile_pipes = 2; + rdev->config.evergreen.max_simds = 2; + rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; diff --git a/queue-3.4/drm-radeon-fix-typo-in-evergreen_mc_resume.patch b/queue-3.4/drm-radeon-fix-typo-in-evergreen_mc_resume.patch new file mode 100644 index 00000000000..a24b7bb5438 --- /dev/null +++ b/queue-3.4/drm-radeon-fix-typo-in-evergreen_mc_resume.patch @@ -0,0 +1,39 @@ +From 695ddeb457584a602f2ba117d08ce37cf6ec1589 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 5 Nov 2012 16:34:58 +0000 +Subject: drm/radeon: fix typo in evergreen_mc_resume() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit 695ddeb457584a602f2ba117d08ce37cf6ec1589 upstream. + +Add missing index that may have led us to enabling +more crtcs than necessary. + +May also fix: +https://bugs.freedesktop.org/show_bug.cgi?id=56139 + +Signed-off-by: Alex Deucher +Reviewed-by: Michel Dänzer +Signed-off-by: Dave Airlie +Cc: Weng Meiling +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -1292,7 +1292,7 @@ void evergreen_mc_resume(struct radeon_d + WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); + + for (i = 0; i < rdev->num_crtc; i++) { +- if (save->crtc_enabled) { ++ if (save->crtc_enabled[i]) { + if (ASIC_IS_DCE6(rdev)) { + tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); + tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; diff --git a/queue-3.4/series b/queue-3.4/series index e39513a964e..e2ec627bf0a 100644 --- a/queue-3.4/series +++ b/queue-3.4/series @@ -155,3 +155,12 @@ modify-uefi-anti-bricking-code.patch x86-efi-fix-dummy-variable-buffer-allocation.patch nbd-fsync-and-kill-block-device-on-shutdown.patch drivers-hv-switch-to-use-mb-instead-of-smp_mb.patch +drm-i915-sdvo-clean-up-connectors-on-intel_sdvo_init-failures.patch +drm-fix-documentation-for-drm_crtc_set_mode.patch +drm-radeon-dce32-use-fractional-fb-dividers-for-high-clocks.patch +drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch +drm-radeon-add-connector-table-for-sam440ep-embedded-board.patch +drm-radeon-add-connector-table-for-mac-g4-silver.patch +drm-nouveau-fix-init-with-agpgart-uninorth.patch +drm-radeon-fix-typo-in-evergreen_mc_resume.patch +drm-i915-close-race-between-processing-unpin-task-and-queueing-the-flip.patch -- 2.47.3