From ed9825cfccf9fbd82fa2d71382840574fec385f8 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Thu, 8 Sep 2022 22:31:39 -0400 Subject: [PATCH] Fixes for 4.19 Signed-off-by: Sasha Levin --- ...fix-incorrect-assignment-of-signed-e.patch | 82 ++++++++++++++++++ ...4-signal-raise-limit-on-stack-frames.patch | 44 ++++++++++ ...-num_gfx_rings-for-gfx-v9_0-rb-setup.patch | 36 ++++++++ ...l2_cntl3-register-not-initialized-co.patch | 33 ++++++++ ...-force-flush-to-delay-work-when-rade.patch | 78 +++++++++++++++++ ...d-missing-pci_disable_device-in-chip.patch | 34 ++++++++ ...me-check-to-prevent-pa2.0-kernels-on.patch | 83 +++++++++++++++++++ ...handle-kmalloc-failure-in-ccio_init_.patch | 58 +++++++++++++ queue-4.19/series | 8 ++ 9 files changed, 456 insertions(+) create mode 100644 queue-4.19/arm64-cacheinfo-fix-incorrect-assignment-of-signed-e.patch create mode 100644 queue-4.19/arm64-signal-raise-limit-on-stack-frames.patch create mode 100644 queue-4.19/drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch create mode 100644 queue-4.19/drm-amdgpu-mmvm_l2_cntl3-register-not-initialized-co.patch create mode 100644 queue-4.19/drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch create mode 100644 queue-4.19/fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch create mode 100644 queue-4.19/parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch create mode 100644 queue-4.19/parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch diff --git a/queue-4.19/arm64-cacheinfo-fix-incorrect-assignment-of-signed-e.patch b/queue-4.19/arm64-cacheinfo-fix-incorrect-assignment-of-signed-e.patch new file mode 100644 index 00000000000..b3e3403a86e --- /dev/null +++ b/queue-4.19/arm64-cacheinfo-fix-incorrect-assignment-of-signed-e.patch @@ -0,0 +1,82 @@ +From 5aac81296e393bb52ed136f750048fe41a8cf481 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Aug 2022 09:46:40 +0100 +Subject: arm64: cacheinfo: Fix incorrect assignment of signed error value to + unsigned fw_level + +From: Sudeep Holla + +[ Upstream commit e75d18cecbb3805895d8ed64da4f78575ec96043 ] + +Though acpi_find_last_cache_level() always returned signed value and the +document states it will return any errors caused by lack of a PPTT table, +it never returned negative values before. + +Commit 0c80f9e165f8 ("ACPI: PPTT: Leave the table mapped for the runtime usage") +however changed it by returning -ENOENT if no PPTT was found. The value +returned from acpi_find_last_cache_level() is then assigned to unsigned +fw_level. + +It will result in the number of cache leaves calculated incorrectly as +a huge value which will then cause the following warning from __alloc_pages +as the order would be great than MAX_ORDER because of incorrect and huge +cache leaves value. + + | WARNING: CPU: 0 PID: 1 at mm/page_alloc.c:5407 __alloc_pages+0x74/0x314 + | Modules linked in: + | CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.19.0-10393-g7c2a8d3ac4c0 #73 + | pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + | pc : __alloc_pages+0x74/0x314 + | lr : alloc_pages+0xe8/0x318 + | Call trace: + | __alloc_pages+0x74/0x314 + | alloc_pages+0xe8/0x318 + | kmalloc_order_trace+0x68/0x1dc + | __kmalloc+0x240/0x338 + | detect_cache_attributes+0xe0/0x56c + | update_siblings_masks+0x38/0x284 + | store_cpu_topology+0x78/0x84 + | smp_prepare_cpus+0x48/0x134 + | kernel_init_freeable+0xc4/0x14c + | kernel_init+0x2c/0x1b4 + | ret_from_fork+0x10/0x20 + +Fix the same by changing fw_level to be signed integer and return the +error from init_cache_level() early in case of error. + +Reported-and-Tested-by: Bruno Goncalves +Signed-off-by: Sudeep Holla +Link: https://lore.kernel.org/r/20220808084640.3165368-1-sudeep.holla@arm.com +Signed-off-by: Will Deacon +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/cacheinfo.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c +index d17414cbb89a8..473935695efb7 100644 +--- a/arch/arm64/kernel/cacheinfo.c ++++ b/arch/arm64/kernel/cacheinfo.c +@@ -47,7 +47,8 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, + + int init_cache_level(unsigned int cpu) + { +- unsigned int ctype, level, leaves, fw_level; ++ unsigned int ctype, level, leaves; ++ int fw_level; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + + for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { +@@ -65,6 +66,9 @@ int init_cache_level(unsigned int cpu) + else + fw_level = acpi_find_last_cache_level(cpu); + ++ if (fw_level < 0) ++ return fw_level; ++ + if (level < fw_level) { + /* + * some external caches not specified in CLIDR_EL1 +-- +2.35.1 + diff --git a/queue-4.19/arm64-signal-raise-limit-on-stack-frames.patch b/queue-4.19/arm64-signal-raise-limit-on-stack-frames.patch new file mode 100644 index 00000000000..2807616a3a9 --- /dev/null +++ b/queue-4.19/arm64-signal-raise-limit-on-stack-frames.patch @@ -0,0 +1,44 @@ +From 4fdd13e4e46ab87c3a09a5bfc0e6440d4d258d4d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 17 Aug 2022 19:23:21 +0100 +Subject: arm64/signal: Raise limit on stack frames + +From: Mark Brown + +[ Upstream commit 7ddcaf78e93c9282b4d92184f511b4d5bee75355 ] + +The signal code has a limit of 64K on the size of a stack frame that it +will generate, if this limit is exceeded then a process will be killed if +it receives a signal. Unfortunately with the advent of SME this limit is +too small - the maximum possible size of the ZA register alone is 64K. This +is not an issue for practical systems at present but is easily seen using +virtual platforms. + +Raise the limit to 256K, this is substantially more than could be used by +any current architecture extension. + +Signed-off-by: Mark Brown +Acked-by: Catalin Marinas +Link: https://lore.kernel.org/r/20220817182324.638214-2-broonie@kernel.org +Signed-off-by: Will Deacon +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/signal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c +index ca565853dea64..bd9b36ab35f0f 100644 +--- a/arch/arm64/kernel/signal.c ++++ b/arch/arm64/kernel/signal.c +@@ -101,7 +101,7 @@ static size_t sigframe_size(struct rt_sigframe_user_layout const *user) + * not taken into account. This limit is not a guarantee and is + * NOT ABI. + */ +-#define SIGFRAME_MAXSZ SZ_64K ++#define SIGFRAME_MAXSZ SZ_256K + + static int __sigframe_alloc(struct rt_sigframe_user_layout *user, + unsigned long *offset, size_t size, bool extend) +-- +2.35.1 + diff --git a/queue-4.19/drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch b/queue-4.19/drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch new file mode 100644 index 00000000000..3bff518821f --- /dev/null +++ b/queue-4.19/drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch @@ -0,0 +1,36 @@ +From c0037ed1812bd588682bb5ae89179cfbcb6993bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 18 Aug 2022 10:47:09 +0800 +Subject: drm/amdgpu: Check num_gfx_rings for gfx v9_0 rb setup. + +From: Candice Li + +[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ] + +No need to set up rb when no gfx rings. + +Signed-off-by: Candice Li +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index d8ae6a23e6133..d36bea68a67e1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1771,7 +1771,8 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) + + gfx_v9_0_tiling_mode_table_init(adev); + +- gfx_v9_0_setup_rb(adev); ++ if (adev->gfx.num_gfx_rings) ++ gfx_v9_0_setup_rb(adev); + gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); + adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); + +-- +2.35.1 + diff --git a/queue-4.19/drm-amdgpu-mmvm_l2_cntl3-register-not-initialized-co.patch b/queue-4.19/drm-amdgpu-mmvm_l2_cntl3-register-not-initialized-co.patch new file mode 100644 index 00000000000..a8bdf00c9e5 --- /dev/null +++ b/queue-4.19/drm-amdgpu-mmvm_l2_cntl3-register-not-initialized-co.patch @@ -0,0 +1,33 @@ +From ed0ef84633bcba1d392ea51597d089018d5bda4a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 23 Aug 2022 14:44:06 +0800 +Subject: drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly + +From: Qu Huang + +[ Upstream commit b8983d42524f10ac6bf35bbce6a7cc8e45f61e04 ] + +The mmVM_L2_CNTL3 register is not assigned an initial value + +Signed-off-by: Qu Huang +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +index c963eec58c702..923bc097a00b2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +@@ -155,6 +155,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); + ++ tmp = mmVM_L2_CNTL3_DEFAULT; + if (adev->gmc.translate_further) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, +-- +2.35.1 + diff --git a/queue-4.19/drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch b/queue-4.19/drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch new file mode 100644 index 00000000000..c1358fbe372 --- /dev/null +++ b/queue-4.19/drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch @@ -0,0 +1,78 @@ +From f16ebcf3abe1e72d36cdb37fec04701fbcf6db08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 11 Aug 2022 15:25:40 +0800 +Subject: drm/radeon: add a force flush to delay work when radeon +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Zhenneng Li + +[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ] + +Although radeon card fence and wait for gpu to finish processing current batch rings, +there is still a corner case that radeon lockup work queue may not be fully flushed, +and meanwhile the radeon_suspend_kms() function has called pci_set_power_state() to +put device in D3hot state. +Per PCI spec rev 4.0 on 5.3.1.4.1 D3hot State. +> Configuration and Message requests are the only TLPs accepted by a Function in +> the D3hot state. All other received Requests must be handled as Unsupported Requests, +> and all received Completions may optionally be handled as Unexpected Completions. +This issue will happen in following logs: +Unable to handle kernel paging request at virtual address 00008800e0008010 +CPU 0 kworker/0:3(131): Oops 0 +pc = [] ra = [] ps = 0000 Tainted: G W +pc is at si_gpu_check_soft_reset+0x3c/0x240 +ra is at si_dma_is_lockup+0x34/0xd0 +v0 = 0000000000000000 t0 = fff08800e0008010 t1 = 0000000000010000 +t2 = 0000000000008010 t3 = fff00007e3c00000 t4 = fff00007e3c00258 +t5 = 000000000000ffff t6 = 0000000000000001 t7 = fff00007ef078000 +s0 = fff00007e3c016e8 s1 = fff00007e3c00000 s2 = fff00007e3c00018 +s3 = fff00007e3c00000 s4 = fff00007fff59d80 s5 = 0000000000000000 +s6 = fff00007ef07bd98 +a0 = fff00007e3c00000 a1 = fff00007e3c016e8 a2 = 0000000000000008 +a3 = 0000000000000001 a4 = 8f5c28f5c28f5c29 a5 = ffffffff810f4338 +t8 = 0000000000000275 t9 = ffffffff809b66f8 t10 = ff6769c5d964b800 +t11= 000000000000b886 pv = ffffffff811bea20 at = 0000000000000000 +gp = ffffffff81d89690 sp = 00000000aa814126 +Disabling lock debugging due to kernel taint +Trace: +[] si_dma_is_lockup+0x34/0xd0 +[] radeon_fence_check_lockup+0xd0/0x290 +[] process_one_work+0x280/0x550 +[] worker_thread+0x70/0x7c0 +[] worker_thread+0x130/0x7c0 +[] kthread+0x200/0x210 +[] worker_thread+0x0/0x7c0 +[] kthread+0x14c/0x210 +[] ret_from_kernel_thread+0x18/0x20 +[] kthread+0x0/0x210 + Code: ad3e0008 43f0074a ad7e0018 ad9e0020 8c3001e8 40230101 + <88210000> 4821ed21 +So force lockup work queue flush to fix this problem. + +Acked-by: Christian König +Signed-off-by: Zhenneng Li +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/radeon/radeon_device.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c +index 59c8a6647ff21..cc1c07963116c 100644 +--- a/drivers/gpu/drm/radeon/radeon_device.c ++++ b/drivers/gpu/drm/radeon/radeon_device.c +@@ -1625,6 +1625,9 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, + if (r) { + /* delay GPU reset to resume */ + radeon_fence_driver_force_completion(rdev, i); ++ } else { ++ /* finish executing delayed work */ ++ flush_delayed_work(&rdev->fence_drv[i].lockup_work); + } + } + +-- +2.35.1 + diff --git a/queue-4.19/fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch b/queue-4.19/fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch new file mode 100644 index 00000000000..5ce980a7c19 --- /dev/null +++ b/queue-4.19/fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch @@ -0,0 +1,34 @@ +From 07a4d8a889f5ca78ad70816abca4038b2396be43 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 16:57:52 +0800 +Subject: fbdev: chipsfb: Add missing pci_disable_device() in + chipsfb_pci_init() + +From: Yang Yingliang + +[ Upstream commit 07c55c9803dea748d17a054000cbf1913ce06399 ] + +Add missing pci_disable_device() in error path in chipsfb_pci_init(). + +Signed-off-by: Yang Yingliang +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + drivers/video/fbdev/chipsfb.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/video/fbdev/chipsfb.c b/drivers/video/fbdev/chipsfb.c +index 413b465e69d8e..7ca149ab86d20 100644 +--- a/drivers/video/fbdev/chipsfb.c ++++ b/drivers/video/fbdev/chipsfb.c +@@ -432,6 +432,7 @@ static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent) + err_release_fb: + framebuffer_release(p); + err_disable: ++ pci_disable_device(dp); + err_out: + return rc; + } +-- +2.35.1 + diff --git a/queue-4.19/parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch b/queue-4.19/parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch new file mode 100644 index 00000000000..b4fd1544882 --- /dev/null +++ b/queue-4.19/parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch @@ -0,0 +1,83 @@ +From ecd1d8423ae183c2219eb6cd1fea7b6951cb514a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 21 Aug 2022 14:49:58 +0200 +Subject: parisc: Add runtime check to prevent PA2.0 kernels on PA1.x machines + +From: Helge Deller + +[ Upstream commit 591d2108f3abc4db9f9073cae37cf3591fd250d6 ] + +If a 32-bit kernel was compiled for PA2.0 CPUs, it won't be able to run +on machines with PA1.x CPUs. Add a check and bail out early if a PA1.x +machine is detected. + +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + arch/parisc/kernel/head.S | 43 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S +index f56cbab64ac10..92bc2fa7e6929 100644 +--- a/arch/parisc/kernel/head.S ++++ b/arch/parisc/kernel/head.S +@@ -22,7 +22,7 @@ + #include + #include + +- .level PA_ASM_LEVEL ++ .level 1.1 + + __INITDATA + ENTRY(boot_args) +@@ -69,6 +69,47 @@ $bss_loop: + stw,ma %arg2,4(%r1) + stw,ma %arg3,4(%r1) + ++#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20) ++ /* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU ++ * and halt kernel if we detect a PA1.x CPU. */ ++ ldi 32,%r10 ++ mtctl %r10,%cr11 ++ .level 2.0 ++ mfctl,w %cr11,%r10 ++ .level 1.1 ++ comib,<>,n 0,%r10,$cpu_ok ++ ++ load32 PA(msg1),%arg0 ++ ldi msg1_end-msg1,%arg1 ++$iodc_panic: ++ copy %arg0, %r10 ++ copy %arg1, %r11 ++ load32 PA(init_stack),%sp ++#define MEM_CONS 0x3A0 ++ ldw MEM_CONS+32(%r0),%arg0 // HPA ++ ldi ENTRY_IO_COUT,%arg1 ++ ldw MEM_CONS+36(%r0),%arg2 // SPA ++ ldw MEM_CONS+8(%r0),%arg3 // layers ++ load32 PA(__bss_start),%r1 ++ stw %r1,-52(%sp) // arg4 ++ stw %r0,-56(%sp) // arg5 ++ stw %r10,-60(%sp) // arg6 = ptr to text ++ stw %r11,-64(%sp) // arg7 = len ++ stw %r0,-68(%sp) // arg8 ++ load32 PA(.iodc_panic_ret), %rp ++ ldw MEM_CONS+40(%r0),%r1 // ENTRY_IODC ++ bv,n (%r1) ++.iodc_panic_ret: ++ b . /* wait endless with ... */ ++ or %r10,%r10,%r10 /* qemu idle sleep */ ++msg1: .ascii "Can't boot kernel which was built for PA8x00 CPUs on this machine.\r\n" ++msg1_end: ++ ++$cpu_ok: ++#endif ++ ++ .level PA_ASM_LEVEL ++ + /* Initialize startup VM. Just map first 16/32 MB of memory */ + load32 PA(swapper_pg_dir),%r4 + mtctl %r4,%cr24 /* Initialize kernel root pointer */ +-- +2.35.1 + diff --git a/queue-4.19/parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch b/queue-4.19/parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch new file mode 100644 index 00000000000..b331de31a0e --- /dev/null +++ b/queue-4.19/parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch @@ -0,0 +1,58 @@ +From 454688a1af3f4e5a166676d73c0f1d20d484e8d3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 12:15:10 +0800 +Subject: parisc: ccio-dma: Handle kmalloc failure in ccio_init_resources() + +From: Li Qiong + +[ Upstream commit d46c742f827fa2326ab1f4faa1cccadb56912341 ] + +As the possible failure of the kmalloc(), it should be better +to fix this error path, check and return '-ENOMEM' error code. + +Signed-off-by: Li Qiong +Signed-off-by: Helge Deller +Signed-off-by: Sasha Levin +--- + drivers/parisc/ccio-dma.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c +index 6efab7a06c5fc..73ee74d6e7a3d 100644 +--- a/drivers/parisc/ccio-dma.c ++++ b/drivers/parisc/ccio-dma.c +@@ -1390,15 +1390,17 @@ ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) + } + } + +-static void __init ccio_init_resources(struct ioc *ioc) ++static int __init ccio_init_resources(struct ioc *ioc) + { + struct resource *res = ioc->mmio_region; + char *name = kmalloc(14, GFP_KERNEL); +- ++ if (unlikely(!name)) ++ return -ENOMEM; + snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); + + ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); + ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); ++ return 0; + } + + static int new_ioc_area(struct resource *res, unsigned long size, +@@ -1552,7 +1554,10 @@ static int __init ccio_probe(struct parisc_device *dev) + return -ENOMEM; + } + ccio_ioc_init(ioc); +- ccio_init_resources(ioc); ++ if (ccio_init_resources(ioc)) { ++ kfree(ioc); ++ return -ENOMEM; ++ } + hppa_dma_ops = &ccio_ops; + dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL); + +-- +2.35.1 + diff --git a/queue-4.19/series b/queue-4.19/series index 142628d9911..b3219bdfb16 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -47,3 +47,11 @@ wifi-mac80211-don-t-finalize-csa-in-ibss-mode-if-state-is-disconnected.patch net-mac802154-fix-a-condition-in-the-receive-path.patch alsa-seq-oss-fix-data-race-for-max_midi_devs-access.patch alsa-seq-fix-data-race-at-module-auto-loading.patch +drm-amdgpu-check-num_gfx_rings-for-gfx-v9_0-rb-setup.patch +drm-radeon-add-a-force-flush-to-delay-work-when-rade.patch +parisc-ccio-dma-handle-kmalloc-failure-in-ccio_init_.patch +parisc-add-runtime-check-to-prevent-pa2.0-kernels-on.patch +arm64-cacheinfo-fix-incorrect-assignment-of-signed-e.patch +arm64-signal-raise-limit-on-stack-frames.patch +fbdev-chipsfb-add-missing-pci_disable_device-in-chip.patch +drm-amdgpu-mmvm_l2_cntl3-register-not-initialized-co.patch -- 2.47.3