From f16fe15c30a04c592c5670f4bce656af59a59c83 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 15 Oct 2015 13:50:58 +0200 Subject: [PATCH] ARM64: zynqmp: Add support for zcu102 It is very similar to zc1751 with DC1 but there are two i2c connected. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/Kconfig | 4 + arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu102.dts | 251 +++++++++++++++++++++++++ configs/xilinx_zynqmp_zcu102_defconfig | 20 ++ include/configs/xilinx_zynqmp_zcu102.h | 35 ++++ 5 files changed, 311 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zcu102.dts create mode 100644 configs/xilinx_zynqmp_zcu102_defconfig create mode 100644 include/configs/xilinx_zynqmp_zcu102.h diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e87d217f47d..e36f2853a4e 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -9,6 +9,9 @@ config TARGET_ZYNQMP_EP config TARGET_ZYNQMP_MINI bool "ZynqMP MINI" +config TARGET_ZYNQMP_ZCU102 + bool "ZynqMP ZCU102" + config TARGET_ZYNQMP_ZC1751_XM015_DC1 bool "ZynqMP ZC1751 XM015 DC1" @@ -29,6 +32,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP default "xilinx_zynqmp_mini" if TARGET_ZYNQMP_MINI + default "xilinx_zynqmp_zcu102" if TARGET_ZYNQMP_ZCU102 default "xilinx_zynqmp_zc1751_xm015_dc1" if TARGET_ZYNQMP_ZC1751_XM015_DC1 default "xilinx_zynqmp_zc1751_xm016_dc2" if TARGET_ZYNQMP_ZC1751_XM016_DC2 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index daee8bc971e..952f459e973 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb \ + zynqmp-zcu102.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts new file mode 100644 index 00000000000..9b6769298a2 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102.dts @@ -0,0 +1,251 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "zynqmp.dtsi" +/ { + model = "ZynqMP ZCU102"; + compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc0 = &rtc; + serial0 = &uart0; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon=cdns,mmio,0xff000000,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x80000000>, <0x8 0x00000000 0x80000000>; + }; +}; + +&amba { + /* clock for uart, can, nand, i2c */ + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + /* Gems */ + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + /* clock for sd/emmc */ + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + /* clock for usb */ + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + /* clock for qspi */ + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem3 { + status = "okay"; + clocks = <&clk125>, <&clk125>, <&clk125>; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@15{ + reg = <15>; + }; +}; + +&gpio { + status = "okay"; + clocks = <&clk100>; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + clocks = <&clk100>; + + i2cswitch@75 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + }; + + tca6416_u61: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + tca6416_u97: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - PS_GTR_LAN_SEL0 + * 1 - PS_GTR_LAN_SEL1 + * 2 - PS_GTR_LAN_SEL2 + * 3 - PS_GTR_LAN_SEL3 + * 4 - PCI_CLK_DIR_SEL + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7 - 17 - not connected + */ + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + clocks = <&clk100>; + eeprom@54 { + compatible = "at,24c64"; /* 24AA64 */ + reg = <0x54>; + }; +}; + +&qspi { + status = "okay"; + clocks = <&clk300 &clk300>; + flash@0 { + compatible = "n25q512a11"; /* Micron MT25QU512ABB8ESF */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + clocks = <&clk250>; +}; + +/* eMMC */ +&sdhci0 { + status = "okay"; + clocks = <&clk200>, <&clk200>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + clocks = <&clk200>, <&clk200>; +}; + +&uart0 { + status = "okay"; + clocks = <&clk100 &clk100>; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + clocks = <&clk250>, <&clk250>; +}; diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig new file mode 100644 index 00000000000..777c87435a3 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_TARGET_ZYNQMP_ZCU102=y +CONFIG_ZYNQMP_QSPI=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h new file mode 100644 index 00000000000..ade4ca999fe --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -0,0 +1,35 @@ +/* + * Configuration for Xilinx ZynqMP zcu102 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU102_H +#define __CONFIG_ZYNQMP_ZCU102_H + +#define CONFIG_ZYNQ_GEM3 +#define CONFIG_ZYNQ_GEM_PHY_ADDR3 15 +#define CONFIG_ZYNQ_GEM_INTERFACE PHY_INTERFACE_MODE_RGMII_ID + +/* #define CONFIG_ZYNQ_SERIAL_UART0 */ +#define CONFIG_ZYNQ_DCC +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_AHCI + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102" + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000 + +#include + +#endif /* __CONFIG_ZYNQMP_ZCU102_H */ -- 2.47.3