From f03899aef44055682fb93ff10473a2fc99071153 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Fri, 26 Jun 2026 18:06:22 +0000 Subject: [PATCH] realtek: add support for Ubiquiti UniFi USW Pro XG 8 PoE Add support for RTL9313-based Ubiquiti UniFi USW Pro XG 8 PoE switch with 8x 10G RJ45 and 2x SFP+ ports. Hardware ======== - RTL9313 switch SoC - 512 MiB RAM - 32 MiB SPI-NOR flash - 8x 100M/1G/2.5G/5G/10G RJ45 ports via 2x RTL8264B - PoE: 8x 802.3bt, 60W per port, 155W total budget - 2x 1G/2.5G/10G SFP+ ports - Buttons: 1x Reset - LEDs: - System LED white/blue - RGBW LED per port - Console: TTL 3.3V, 115200 8N1, populated 4-pin header (device must be opened to access header) - Etherlighting feature (lighting patterns and color control) - Vendor firmware: U-Boot + LEDE-based Ubiquiti OS MAC address =========== Single MAC address in EEPROM partition, applied to all ports. Known issues ============ - PoE not available, depends on WIP Realtek PSE MCU driver - Etherlighting not controllable, driver WIP. Port LEDs for link work though. By default, the controller keeps the LEDs in a breathing state, gated by the link state delivered by the Realtek SoC. Disclaimer ========== Stock firmware uses a dual-bank layout (kernel0/kernel1, ~15 MiB each). OpenWrt replaces both banks with a single contiguous firmware partition. Flashing OpenWrt overwrites both stock kernel slots; U-Boot remains intact and can be used for recovery. Installation ============ 1. Enable SSH on the stock UniFi OS and log in with user account. (at this stage you may make backups of the flash, just to be sure) 2. Copy the OpenWrt sysupgrade image to /tmp on the switch (e.g. via scp). 3. Adjust IMG below to point at the copied file, then run the block as a whole. It writes kernel0, splits into kernel1 if the image is larger than that slot (otherwise invalidates kernel1 so U-Boot cannot pick a stale bank), and reboots: IMG=/tmp/openwrt-realtek-rtl931x-ubnt_usw-pro-xg-8-poe-squashfs-sysupgrade.bin K0_BLOCKS=$((0xec0000 / 0x10000)) dd if="$IMG" of=/dev/mtdblock2 bs=64k count=$K0_BLOCKS conv=fsync if [ "$(wc -c < "$IMG")" -gt $((0xec0000)) ]; then dd if="$IMG" of=/dev/mtdblock3 bs=64k skip=$K0_BLOCKS conv=fsync else dd if=/dev/zero of=/dev/mtdblock3 bs=64k count=1 conv=fsync fi sync Then reboot the switch, it comes up in OpenWrt after reboot. You may also install the image in any other way, just make sure to write it to the kernel0 partition and if the image is larger than 16MiB, write the rest to the kernel1 partition, otherwise invalidate it so U-Boot cannot boot from the second bank. 4. It is recommended to modify the bootcmd to speedup the boot and prevent any issues due to the dual-boot selection. Since U-Boot by default uses bootubnt which does a lot of (unneeded) RTK initialization, quite some time passes until Linux is started. Additionally, the U-boot logic fiddles with some bits on flash which causes JFFS2 errors in OpenWrt. While this doesn't seem to cause issues yet, be defensive and set the bootcmd to: bootm 0xb4150000 This directly boots the uImage from flash, without doing all the initialization. OpenWrt is able to bootstrap the networking completely on its own. It does not matter which bank stock booted from when the dd block runs: both banks are touched in the same pass (kernel0 written, kernel1 either written or invalidated). With kernel1 invalidated, U-Boot's internal fallback kicks in and permanently switches to kernel0 on the next boot, so the device stays on OpenWrt as long as kernel0 is bootable. Recovery ======== Since the installation procedure invalidates or partially overwrites the second bank, recovery requires serial console access (see Hardware above for pinout). 1. Interrupt U-Boot autoboot by spamming a key during early boot to drop into the U-Boot prompt. 2. Bring up networking: rtk network on 3. Transfer an OpenWrt initramfs image via TFTP and boot it: tftpboot 0x82000000 : bootm 0x82000000 4. From the running initramfs OpenWrt, do a sysupgrade to reflash OpenWrt or whatever you want to recover. There is no need for the complicated procedure from installation since OpenWrt sees the firmware partition already as a whole. Return to stock firmware ======================== There is no fully-supported revert path. The stock firmware blob is a Ubiquiti UBNT archive (header + parts, see firmware-utils' fw.h) that embeds a u-boot and a kernel0 uImage payload; only the latter is relevant when writing back to the kernel partitions. The snippet below extracts the kernel0 uImage from such a blob by locating the uImage magic and using the size carried in the uImage header itself, without parsing any UBNT framing. It is provided as a best-effort starting point; verify the result before flashing, otherwise you're on your own: BLOB=US3.rtl93xx_7.4.1+X.Y.Z.bin OFF=$(grep -aboF $'\x27\x05\x19\x56' "$BLOB" | head -1 | cut -d: -f1) SIZE=$(( $(dd if="$BLOB" bs=1 skip=$((OFF + 12)) count=4 2>/dev/null \ | hexdump -e '1/4 "%u"') + 64 )) dd if="$BLOB" of=kernel0.uImage bs=1 skip="$OFF" count="$SIZE" Once you have a clean uImage, it can be written to the kernel partition from within OpenWrt. If you adjusted the bootcmd during installation, make sure to restore it to the default "bootcmd=bootubnt". After a reboot, Ubiquiti's firmware should boot. Or, if you did backups of the flash before, just write the backup to the flash. Link: https://github.com/openwrt/openwrt/pull/24010 Signed-off-by: Jonas Jelonek --- .../realtek/base-files/etc/board.d/02_network | 1 + .../dts/rtl9313_ubnt_usw-pro-xg-8-poe.dts | 291 ++++++++++++++++++ target/linux/realtek/image/rtl931x.mk | 10 + 3 files changed, 302 insertions(+) create mode 100644 target/linux/realtek/dts/rtl9313_ubnt_usw-pro-xg-8-poe.dts diff --git a/target/linux/realtek/base-files/etc/board.d/02_network b/target/linux/realtek/base-files/etc/board.d/02_network index 52cf1cf2535..c7a23d41cc6 100644 --- a/target/linux/realtek/base-files/etc/board.d/02_network +++ b/target/linux/realtek/base-files/etc/board.d/02_network @@ -95,6 +95,7 @@ realtek_setup_macs() plasmacloud,psx10|\ plasmacloud,psx28|\ sirivision,sr-st3408f|\ + ubnt,usw-pro-xg-8-poe|\ zyxel,gs1920-24hp-v2) lan_mac="$(get_mac_label)" ;; diff --git a/target/linux/realtek/dts/rtl9313_ubnt_usw-pro-xg-8-poe.dts b/target/linux/realtek/dts/rtl9313_ubnt_usw-pro-xg-8-poe.dts new file mode 100644 index 00000000000..b853ee1d172 --- /dev/null +++ b/target/linux/realtek/dts/rtl9313_ubnt_usw-pro-xg-8-poe.dts @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "rtl931x.dtsi" + +#include +#include +#include +#include +#include + +/ { + compatible = "ubnt,usw-pro-xg-8-poe", "realtek,rtl9313-soc"; + model = "UniFi USW Pro XG 8 PoE"; + + aliases { + label-mac-device = ðernet0; + led-boot = &led_sys_white; + led-failsafe = &led_sys_white; + led-running = &led_sys_blue; + led-upgrade = &led_sys_white; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>, /* first 256 MiB */ + <0x90000000 0x10000000>; /* remaining 256 MiB */ + }; + + keys { + compatible = "gpio-keys"; + + key-reset { + label = "reset"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_disable_sys_led>; + + led_sys_blue: led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + led_sys_white: led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + + led_set: led_set@0 { + compatible = "realtek,rtl9300-leds"; + clock-frequency = <1250000>; + active-low; + + /* + * selects all speed modes to trigger a LED, two slots. This doesn't correspond + * fully to actual LED behavior. The serial stream is fed into the Etherlighting + * MCU which translates that into the LEDs, managing color, behavior etc. in + * addition. + */ + led_set0 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G | + RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M | + RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G | + RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M | + RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>; + }; + + sfp1: sfp-p1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio2 2 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp-p2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + los-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x140000>; + read-only; + }; + + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x10000>; + }; + + /* + * Vendor layout has two kernel partitions: + * (1) <0x150000 0xec0000> = "kernel0" + * (2) <0x1010000 0xed0000> = "kernel1" + */ + partition@150000 { + label = "firmware"; + reg = <0x150000 0x1d90000>; + compatible = "openwrt,uimage", "denx,uimage"; + }; + + partition@1ee0000 { + label = "cdata"; + reg = <0x1ee0000 0x10000>; + }; + + partition@1ef0000 { + label = "cfg"; + reg = <0x1ef0000 0x100000>; + }; + + partition@1ff0000 { + label = "EEPROM"; + reg = <0x1ff0000 0x10000>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + factory_macaddr: macaddr@0 { + compatible = "mac-base"; + reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; +}; + +ðernet0 { + nvmem-cells = <&factory_macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_disable_jtag>; + + /* + * GPIO 1 is the global reset pin shared by all PHYs across all MDIO + * buses. It is intentionally not declared as reset-gpios on any bus: + * the MDIO driver / phylink only support a reset GPIO per bus, not on + * the parent controller. Attaching it to a single bus would still reset + * the PHYs on the other buses as a side effect, leaving their software + * state out of sync with the hardware and likely breaking them. + */ + phy_reset_hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "phy-reset"; + }; +}; + +&i2c_mst1 { + status = "okay"; + + i2c_sfp1: i2c@0 { reg = <0>; }; + i2c_sfp2: i2c@1 { reg = <1>; }; + i2c7: i2c@7 { reg = <7>; }; /* Etherlighting MCU at 0x66 */ + + i2c8: i2c@8 { + reg = <8>; + + adt7475@2e { + compatible = "adi,adt7475"; + reg = <0x2e>; + }; + }; +}; + +&i2c_mst2 { + status = "okay"; + + i2c5: i2c@5 { + reg = <5>; + + gpio1: gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c6: i2c@6 { reg = <6>; }; /* PoE MCU at 0x20 */ +}; + +&mdio_ctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_enable_mdc_mdio_0>; +}; + +&mdio_bus0 { + /* RTL8264B */ + ethernet-phy-package@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + PHY_C45(0, 0) + PHY_C45(8, 1) + PHY_C45(16, 2) + PHY_C45(24, 3) + }; + + /* RTL8264B */ + ethernet-phy-package@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + PHY_C45(32, 4) + PHY_C45(40, 5) + PHY_C45(48, 6) + PHY_C45(50, 7) + }; +}; + +&switch0 { + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii) + SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii) + SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii) + SWITCH_PORT_LED(24, 4, 5, 0, 0, usxgmii) + SWITCH_PORT_LED(32, 5, 6, 0, 0, usxgmii) + SWITCH_PORT_LED(40, 6, 7, 0, 0, usxgmii) + SWITCH_PORT_LED(48, 7, 8, 0, 0, usxgmii) + SWITCH_PORT_LED(50, 8, 9, 0, 0, usxgmii) + + SWITCH_PORT_SFP(54, 9, 12, 0, 1) + SWITCH_PORT_SFP(55, 10, 13, 0, 2) + + /* CPU port */ + port@56 { + ethernet = <ðernet0>; + reg = <56>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + diff --git a/target/linux/realtek/image/rtl931x.mk b/target/linux/realtek/image/rtl931x.mk index 3d6607a1f00..3afa8303563 100644 --- a/target/linux/realtek/image/rtl931x.mk +++ b/target/linux/realtek/image/rtl931x.mk @@ -43,6 +43,16 @@ define Device/plasmacloud_psx28 endef TARGET_DEVICES += plasmacloud_psx28 +define Device/ubnt_usw-pro-xg-8-poe + SOC := rtl9313 + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi USW Pro XG 8 PoE + IMAGE_SIZE := 30272k + DEVICE_PACKAGES := rtl826x-firmware kmod-hwmon-adt7475 + $(Device/kernel-lzma) +endef +TARGET_DEVICES += ubnt_usw-pro-xg-8-poe + define Device/xikestor_sks8300-12x-v1 SOC := rtl9313 DEVICE_VENDOR := XikeStor -- 2.47.3