git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 2ac0b029a04b673ce83b5089368f467c5dca720c Mon Sep 17 00:00:00 2001
   2 From: Marc Kleine-Budde <mkl@pengutronix.de>
   3 Date: Thu, 10 Jun 2021 15:46:16 +0200
   4 Subject: iio: ltr501: mark register holding upper 8 bits of ALS_DATA{0,1} and PS_DATA as volatile, too
   5
   6 From: Marc Kleine-Budde <mkl@pengutronix.de>
   7
   8 commit 2ac0b029a04b673ce83b5089368f467c5dca720c upstream.
   9
  10 The regmap is configured for 8 bit registers, uses a RB-Tree cache and
  11 marks several registers as volatile (i.e. do not cache).
  12
  13 The ALS and PS data registers in the chip are 16 bit wide and spans
  14 two regmap registers. In the current driver only the base register is
  15 marked as volatile, resulting in the upper register only read once.
  16
  17 Further the data sheet notes:
  18
  19 | When the I2C read operation starts, all four ALS data registers are
  20 | locked until the I2C read operation of register 0x8B is completed.
  21
  22 Which results in the registers never update after the 2nd read.
  23
  24 This patch fixes the problem by marking the upper 8 bits of the ALS
  25 and PS registers as volatile, too.
  26
  27 Fixes: 2f2c96338afc ("iio: ltr501: Add regmap support.")
  28 Reported-by: Oliver Lang <Oliver.Lang@gossenmetrawatt.com>
  29 Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
  30 Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
  31 Tested-by: Nikita Travkin <nikita@trvn.ru> # ltr559
  32 Link: https://lore.kernel.org/r/20210610134619.2101372-2-mkl@pengutronix.de
  33 Cc: <Stable@vger.kernel.org>
  34 Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
  35 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  36
  37 ---
  38  drivers/iio/light/ltr501.c |    6 ++++++
  39  1 file changed, 6 insertions(+)
  40
  41 --- a/drivers/iio/light/ltr501.c
  42 +++ b/drivers/iio/light/ltr501.c
  43 @@ -35,9 +35,12 @@
  44  #define LTR501_PART_ID 0x86
  45  #define LTR501_MANUFAC_ID 0x87
  46  #define LTR501_ALS_DATA1 0x88 /* 16-bit, little endian */
  47 +#define LTR501_ALS_DATA1_UPPER 0x89 /* upper 8 bits of LTR501_ALS_DATA1 */
  48  #define LTR501_ALS_DATA0 0x8a /* 16-bit, little endian */
  49 +#define LTR501_ALS_DATA0_UPPER 0x8b /* upper 8 bits of LTR501_ALS_DATA0 */
  50  #define LTR501_ALS_PS_STATUS 0x8c
  51  #define LTR501_PS_DATA 0x8d /* 16-bit, little endian */
  52 +#define LTR501_PS_DATA_UPPER 0x8e /* upper 8 bits of LTR501_PS_DATA */
  53  #define LTR501_INTR 0x8f /* output mode, polarity, mode */
  54  #define LTR501_PS_THRESH_UP 0x90 /* 11 bit, ps upper threshold */
  55  #define LTR501_PS_THRESH_LOW 0x92 /* 11 bit, ps lower threshold */
  56 @@ -1328,9 +1331,12 @@ static bool ltr501_is_volatile_reg(struc
  57  {
  58         switch (reg) {
  59         case LTR501_ALS_DATA1:
  60 +       case LTR501_ALS_DATA1_UPPER:
  61         case LTR501_ALS_DATA0:
  62 +       case LTR501_ALS_DATA0_UPPER:
  63         case LTR501_ALS_PS_STATUS:
  64         case LTR501_PS_DATA:
  65 +       case LTR501_PS_DATA_UPPER:
  66                 return true;
  67         default:
  68                 return false;