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(parent: d8f8373) | patch
staging: media: tegra-video: tegra20: increase maximum VI clock frequency
authorSvyatoslav Ryhel <clamor95@gmail.com>
Tue, 3 Mar 2026 08:42:35 +0000 (10:42 +0200)
committerHans Verkuil <hverkuil+cisco@kernel.org>
Thu, 19 Mar 2026 07:18:36 +0000 (08:18 +0100)
commit071fa83ded5e0d369e3dd2af2afb70e09b39336c
treeb1f2c3750cae7eb41604518a9abdc6ab07004932tree | snapshot
parentd8f8373f1a319830e54791ee0e18aed1e0f2bd56commit | diff
staging: media: tegra-video: tegra20: increase maximum VI clock frequency

Increase maximum VI clock frequency to 450MHz to allow correct work with
high resolution camera sensors.

Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
drivers/staging/media/tegra-video/tegra20.c diff | blob | blame | history
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