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target/arm: GICv5 cpuif: Implement PPI enable register
authorPeter Maydell <peter.maydell@linaro.org>
Fri, 27 Mar 2026 11:16:34 +0000 (11:16 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 7 May 2026 14:13:47 +0000 (15:13 +0100)
commit2f36257492dcd66438f2f00560b37fd9044ef00a
tree89262e9c0ee6b9d84b0b8406e6c8a3f9aebe6f2ftree | snapshot
parent585dad9e79e1d64075e99448ee34adbeeeeea056commit | diff
target/arm: GICv5 cpuif: Implement PPI enable register

Implement the GICv5 register which holds the enable state of PPIs:
ICC_PPI_ENABLER<n>_EL1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-id: 20260327111700.795099-40-peter.maydell@linaro.org
target/arm/cpu.h diff | blob | blame | history
target/arm/tcg/gicv5-cpuif.c diff | blob | blame | history
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