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(parent: 10d187b) | patch
drm/i915/cx0: Drop C20 25.175 MHz rate
authorMika Kahola <mika.kahola@intel.com>
Mon, 19 Jan 2026 09:37:54 +0000 (09:37 +0000)
committerMika Kahola <mika.kahola@intel.com>
Tue, 20 Jan 2026 08:53:01 +0000 (10:53 +0200)
commit4fa244583e77fba2388f05a44f400f44f79da396
treedd1190c8e7813f6341fca1e98c34a4450205b7dftree | snapshot
parent10d187b3560a45e6cf829a9c52ee54c6dfb42f3acommit | diff
drm/i915/cx0: Drop C20 25.175 MHz rate

Drop C20 25.175 MHz PLL table as with these
PLL dividers the port clock will be incorrectly
calculated to 25.2 MHz. For 25.175 MHz rate the
PLl dividers are calculated algorithmically making
PLL table for this rate redundant.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-14-mika.kahola@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c diff | blob | blame | history
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