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drm/i915/cx0: Create macro around PLL tables
authorMika Kahola <mika.kahola@intel.com>
Mon, 19 Jan 2026 09:37:47 +0000 (09:37 +0000)
committerMika Kahola <mika.kahola@intel.com>
Tue, 20 Jan 2026 08:52:52 +0000 (10:52 +0200)
commit52801b2eb532e8516e2366c4f67ef7cd022ef4ba
treebc3837e5142e2635611fdb03ccf6903a052455eetree | snapshot
parent81152791701fdfa1bb9adff846a6eef888021227commit | diff
drm/i915/cx0: Create macro around PLL tables

Create macro for storing PLL dividers with table name
and clock rate.

v2: Preserve the terminating {} in each PLL table.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-7-mika.kahola@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c diff | blob | blame | history
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