RISC-V: Add another combine pattern for vfmin/max on cost model

RISC-V: Add another combine pattern for vfmin/max on cost model

The recent change introduce another form of vfmin/max, which is
more "literal" compare the previous one.  The related vx_vf/vf*
test cases also failed due to this change.  Thus, add the pattern
to make the test case happy.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
* Fix the vx_vf/vf* testcases.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*literal_v<ieee_fmaxmin_op>_vf_<mode>):
	Add new pattern for vfmax/min combine to fx.

Signed-off-by: Pan Li <pan2.li@intel.com>