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cxl/test: Update test code for event records to CXL spec rev 3.1
authorShiju Jose <shiju.jose@huawei.com>
Sat, 11 Jan 2025 09:17:56 +0000 (09:17 +0000)
committerDave Jiang <dave.jiang@intel.com>
Mon, 13 Jan 2025 16:33:21 +0000 (09:33 -0700)
commit6cdbd84dc42b5f7e61c0aed67596efa0f4406a20
tree36ef33b63ec0c4d188cf60b683484e410ebe6399tree | snapshot
parent4c6e20eb564e0d77497f452ab1ae1b40b1de3ab7commit | diff
cxl/test: Update test code for event records to CXL spec rev 3.1

Update test code for General Media, DRAM, Memory Module Event
Records to CXL spec rev 3.1.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Link: https://patch.msgid.link/20250111091756.1682-7-shiju.jose@huawei.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
tools/testing/cxl/test/mem.c diff | blob | blame | history
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