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drm/i915/lt_phy: Add lane_count to PLL state
authorMika Kahola <mika.kahola@intel.com>
Thu, 12 Mar 2026 08:06:38 +0000 (08:06 +0000)
committerMika Kahola <mika.kahola@intel.com>
Tue, 24 Mar 2026 07:45:49 +0000 (09:45 +0200)
commit6e1c3b80ee801d1450a20a5420e79f9460bc5f0b
tree2014863acd696b21fde48beaeb9d40a94f078399tree | snapshot
parentf52bbb00deaaa137271217e158537151f6c792b6commit | diff
drm/i915/lt_phy: Add lane_count to PLL state

Cache lane count as part of PLL state.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-6-mika.kahola@intel.com
drivers/gpu/drm/i915/display/intel_dpll_mgr.h diff | blob | blame | history
drivers/gpu/drm/i915/display/intel_lt_phy.c diff | blob | blame | history
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