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(parent: b50c2a7) | patch
clk: zynq: Show watchdog clock rate properly
authorMichal Simek <michal.simek@xilinx.com>
Wed, 21 Feb 2018 14:06:20 +0000 (15:06 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 21 Feb 2018 15:33:08 +0000 (16:33 +0100)
commit6f3fa736582083fe720fccc4e052640c521ebdce
tree546bc828c42a97ddacdfc87dd4d22d35d87b3675tree | snapshot
parentb50c2a7bd4430b5dbc077c06b40144dcadd2631ccommit | diff
clk: zynq: Show watchdog clock rate properly

watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/clk/clk_zynq.c diff | blob | blame | history
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