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serial: uartlite: Fix uninitialized ret in debug uartlite
authorAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Tue, 1 Dec 2020 07:34:47 +0000 (00:34 -0700)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 2 Feb 2021 11:31:28 +0000 (12:31 +0100)
commit9a545a478c7b24ee8c8a7880672d105e0316bc6e
treeb37d622aa5f6b7833d17acf8e4a7e78ec12a1692tree | snapshot
parentc4fddedc48f336eabc4ce3f74940e6aa372de18ccommit | diff
serial: uartlite: Fix uninitialized ret in debug uartlite

Endianness detection is checked against uninitialized ret variable.
Assign ret with read value from status register to fix this.

Fixes: 31a359f87eaa ("serial: uartlite: Add support to work with any endianness")
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: upstream (e5e8bbd25a499e65e7403b0b054fe35abe5187b3)
drivers/serial/serial_xuartlite.c diff | blob | blame | history
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