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drm/i915/display: Disable DMG Clock Gating
authorSuraj Kandpal <suraj.kandpal@intel.com>
Thu, 22 Jan 2026 03:18:18 +0000 (08:48 +0530)
committerSuraj Kandpal <suraj.kandpal@intel.com>
Tue, 27 Jan 2026 03:56:35 +0000 (09:26 +0530)
commitad381460c90bd3b9d39a5160df0b8b446b098736
tree093eb9fad15461a593702be3747fd069f9d224aatree | snapshot
parentbbde2759de1b85ae8c45281f251cdf61cd23fa7fcommit | diff
drm/i915/display: Disable DMG Clock Gating

Incorrect clock is connected to DMG registers.
Disable DMG Clock gating during display initialization.

WA: 22021451799
Bspec: 69095
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patch.msgid.link/20260122031818.703590-1-suraj.kandpal@intel.com
drivers/gpu/drm/i915/display/intel_display_wa.c diff | blob | blame | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
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