]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
authorStafford Horne <shorne@gmail.com>
Tue, 14 Jan 2025 17:07:21 +0000 (17:07 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 7 Mar 2025 15:45:48 +0000 (16:45 +0100)
commitd82826201ffe4f8eb0689dea32f3ef058852529c
treeb1c5cc083a6a53f3fa0e19d3a9fb1e0b2174c0e4
parent32fb5ec825f6f76bc28902181c65429a904a07fe
rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm

commit 713e788c0e07e185fd44dd581f74855ef149722f upstream.

When working on OpenRISC support for restartable sequences I noticed
and fixed these two issues with the riscv support bits.

 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
   passed to the macro.  Fix this by adding 'inc' to the list of macro
   arguments.
 2 The inline asm input constraints for 'inc' and 'off' use "er",  The
   riscv gcc port does not have an "e" constraint, this looks to be
   copied from the x86 port.  Fix this by just using an "r" constraint.

I have compile tested this only for riscv.  However, the same fixes I
use in the OpenRISC rseq selftests and everything passes with no issues.

Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")
Signed-off-by: Stafford Horne <shorne@gmail.com>
Tested-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Acked-by: Shuah Khan <skhan@linuxfoundation.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20250114170721.3613280-1-shorne@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
tools/testing/selftests/rseq/rseq-riscv-bits.h
tools/testing/selftests/rseq/rseq-riscv.h