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soc/tegra: pmc: Rename has_impl_33v_pwr flag
authorJon Hunter <jonathanh@nvidia.com>
Wed, 25 Mar 2026 19:25:59 +0000 (19:25 +0000)
committerThierry Reding <treding@nvidia.com>
Sat, 28 Mar 2026 00:02:39 +0000 (01:02 +0100)
commitdb3c16b2b90b0f56a94f9780f9dd10b50b648860
tree0fc128f04393035aedc2a27d263327f4178ad83atree | snapshot
parentedded7a9033a77c9b8a66176daa5e0b601e7c474commit | diff
soc/tegra: pmc: Rename has_impl_33v_pwr flag

The flag 'has_impl_33v_pwr' is now only used to determine if we need to
set the write-enable bit before we can set the bit to select if 3.3V IO
is used or not. Therefore, rename the flag to 'has_io_pad_wren' to
indicate that the SoC supports the write-enable register.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/soc/tegra/pmc.c diff | blob | blame | history
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