aarch64: fp8 convert and scale - add sve2 insn variants

aarch64: fp8 convert and scale - add sve2 insn variants

Add the SVE2 variant of the FP8 convert and scale instructions,
enabled at assembly-time using the `+sve2+fp8' architectural
extension flag.  More specifically, support is added for the
following instructions:

FP8 convert to BFloat16 (bottom/top):
-------------------------------------

  - bf1cvt Z<d>.H, Z<n>.B
  - bf2cvt Z<d>.H, Z<n>.B
  - bf1cvtlt Z<d>.H, Z<n>.B
  - bf2cvtlt Z<d>.H, Z<n>.B

FP8 convert to half-precision (bottom/top):
-------------------------------------------

  - f1cvt Z<d>.H, Z<n>.B
  - f2cvt Z<d>.H, Z<n>.B
  - f1cvtlt Z<d>.H, Z<n>.B
  - f2cvtlt Z<d>.H, Z<n>.B

BFloat16/half-precision convert, narrow and
interleave to FP8:
-------------------------------------------

  - bfcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
  - fcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }

Single-precision convert, narrow and interleave
to FP8 (bottom/top):
-----------------------------------------------

  - fcvtnb Z<d>.B, { Z<n>1.S - Z<n>2.S }
  - fcvtnt Z<d>.B, { Z<n>1.S - Z<n>2.S }