[PR target/124559][RISC-V] Improve RISC-V constant synthesis for some HImode constants

So this is a trivial little bug we found doing some comparisons against LLVM.

For the function sub2 in load-immediate.c we get this code:

        li      a5,-32768
        sh      a5,0(a0)
        xori    a5,a5,-1
        sh      a5,0(a1)

Note carefully that li+xori.  There's a slightly better sequence here from an
encoding standpoint.  Instead of using xori we can adjust the synthesis
sequence to target an "addi" for that statement and in doing so we can save two
code bytes of space.

The xori sequence was used because we can't do this in gcc:

(set (dest:HI) (const_int 0x8000))

We're in HI mode so the constant must be sign extended from bit 15 to a
HOST_WIDE_INT.

Fixing this isn't hard.  The key is realizing the vast majority of the time we
really don't want/need to load in HImode and in fact we're typically going to
be generating objects in word_mode.  So instead of passing in the pre-promoted
mode, pass in the post-promoted mode.

That's fine and good with one caveat.   CSE fails to use NEG/NOT to derive a
new constant from an older constant, even if the cost is smaller, which caused
a code quality regression elsewhere on the RISC-V port.  So this patch adjusts
CSE ever-so-slightly to allow it to derive constants from a previous constant
using NOT/NEG in a fairly obvious way.

This has been in my tester for a while, so it's been through the usual
bootstrap & regression test on the Pioneer, BPI, x86 and aarch64 and others as
well as testing across the various embedded targets.

Waiting on pre-commit testing to do its thing.

	PR target/124559
gcc/
	* config/riscv/riscv-protos.h (riscv_move_integer): Drop mode argument.
	* config/riscv/riscv.cc (riscv_move_integer): Pass mode after promotions
	to riscv_build_integer.  All callers changed.
	* config/riscv/riscv.md: Corresponding changes.
	* cse.cc (cse_insn): Try to derive one constant from another using NOT/NEG.

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index dd029c704133704b10a829c24d62fbd530713e68..494feb4458de1c816b3fcbcb8fd5d3b2b201517a 100644 (file)
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -119,7 +119,7 @@ extern rtx riscv_emit_move (rtx, rtx);
 extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
 extern bool riscv_split_symbol_type (enum riscv_symbol_type);
 extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
-extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode);
+extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
 extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
 extern rtx riscv_subword (rtx, bool);
 extern bool riscv_split_64bit_move_p (rtx, rtx);

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 97272b4349a6d99844d71703f6a0374cbef4a794..b936e3c272fc7eac249bb2ed2b7e1970001f25fc 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1736,15 +1736,15 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode)
   bool eq_neg = (loval == hival) && ((loval & 0x80000000) != 0);
 
   if (eq_neg)
-    riscv_move_integer (lo, lo, ~loval & 0xffffffff, mode);
+    riscv_move_integer (lo, lo, ~loval & 0xffffffff);
   else
-    riscv_move_integer (lo, lo, loval, mode);
+    riscv_move_integer (lo, lo, loval);
 
   if (loval == hival)
       hi = gen_rtx_ASHIFT (mode, lo, GEN_INT (32));
   else
     {
-      riscv_move_integer (hi, hi, hival, mode);
+      riscv_move_integer (hi, hi, hival);
       hi = gen_rtx_ASHIFT (mode, hi, GEN_INT (32));
     }
 
@@ -3275,8 +3275,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
    is the original src mode before promotion.  */
 
 void
-riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
-                   machine_mode orig_mode)
+riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value)
 {
   struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
   machine_mode mode;
@@ -3284,9 +3283,10 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
   rtx x = NULL_RTX;
 
   mode = GET_MODE (dest);
-  /* We use the original mode for the riscv_build_integer call, because HImode
-     values are given special treatment.  */
-  num_ops = riscv_build_integer (codes, value, orig_mode, can_create_pseudo_p ());
+  /* This originally passed in a mode prior to promotions, but what we really
+     need to do is pass in the mode of the destination, that's what ultimately
+     determines how a constant needs to be canonicalized.  */
+  num_ops = riscv_build_integer (codes, value, mode, can_create_pseudo_p ());
 
   if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */
       && num_ops >= riscv_split_integer_cost (value))
@@ -3383,7 +3383,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
   /* Split moves of big integers into smaller pieces.  */
   if (splittable_const_int_operand (src, mode))
     {
-      riscv_move_integer (dest, dest, INTVAL (src), mode);
+      riscv_move_integer (dest, dest, INTVAL (src));
       return;
     }
 
@@ -3970,7 +3970,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
          if (splittable_const_int_operand (src, mode))
            {
              reg = gen_reg_rtx (promoted_mode);
-             riscv_move_integer (reg, reg, INTVAL (src), mode);
+             riscv_move_integer (reg, reg, INTVAL (src));
            }
          else
            reg = force_reg (promoted_mode, src);

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6b5f824109e6c624bef46a1d16c8695e693cd0e4..ee44132291f0eb4e5393e20ffa9ad8debb2457df 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2504,8 +2504,7 @@
   ""
   [(const_int 0)]
 {
-  riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]),
-                     <GPR:MODE>mode);
+  riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]));
   DONE;
 })
 
@@ -2538,8 +2537,7 @@
   "&& 1"
   [(const_int 0)]
 {
-  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
-                      <MODE>mode);
+  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]));
   DONE;
 }
 [(set_attr "type" "move")])

diff --git a/gcc/cse.cc b/gcc/cse.cc
index 25b2bf500a96fc448b6720bb0df3e3f2f271f9e0..b4b39e3ebf81b10376618edf9493ebb96c8d7752 100644 (file)
--- a/gcc/cse.cc
+++ b/gcc/cse.cc
@@ -4980,6 +4980,34 @@ cse_insn (rtx_insn *insn)
            }
        }
 
+      /* If SRC_EQV is a CONST_INT, try looking up some related
+        constants (logical and arithmetic negation).  Those may
+        ultimately be cheaper to re-use.  */
+      if (GET_CODE (src) != CONST_INT
+         && GET_CODE (src) != REG
+         && GET_CODE (src) != SUBREG
+         && src_const
+         && GET_CODE (src_const) == CONST_INT)
+       {
+         rtx trial_rtx = GEN_INT (~UINTVAL (src_const));
+         struct table_elt *tmp = lookup (trial_rtx, HASH (trial_rtx, mode), mode);
+         rtx_code code = NOT;
+         if (!tmp)
+           {
+             trial_rtx = GEN_INT (-UINTVAL (src_const));
+             tmp = lookup (trial_rtx, HASH (trial_rtx, mode), mode);
+             code = NEG;
+           }
+
+         if (tmp)
+           {
+             src_related = gen_rtx_fmt_e (code, mode, tmp->first_same_value->exp);
+             src_eqv_here = src_related;
+             src_related_is_const_anchor = true;
+           }
+
+       }
+
       /* See if a MEM has already been loaded with a widening operation;
         if it has, we can use a subreg of that.  Many CISC machines
         also have such operations, but this is only likely to be