Refresh the patches for 6.18 so they apply.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
-@@ -147,7 +147,7 @@ config RESET_LPC18XX
+@@ -170,7 +170,7 @@ config RESET_LPC18XX
config RESET_MCHP_SPARX5
- bool "Microchip Sparx5 reset driver"
-- depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
-+ depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || COMPILE_TEST
+ tristate "Microchip Sparx5 reset driver"
+- depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
++ depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
default y if SPARX5_SWITCH
select MFD_SYSCON
help
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
-@@ -2259,12 +2259,29 @@ static int __maybe_unused atmel_xdmac_ru
+@@ -2257,12 +2257,29 @@ static int __maybe_unused atmel_xdmac_ru
return clk_enable(atxdmac->clk);
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
-@@ -2280,7 +2297,10 @@ static int at_xdmac_probe(struct platfor
+@@ -2278,7 +2295,10 @@ static int at_xdmac_probe(struct platfor
* of channels to do the allocation.
*/
reg = readl_relaxed(base + AT_XDMAC_GTYPE);
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
-@@ -396,6 +396,8 @@ static int sparx5_create_port(struct spa
+@@ -395,6 +395,8 @@ static int sparx5_create_port(struct spa
spx5_port->phylink = phylink;
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
-@@ -602,7 +602,7 @@ config SENSORS_I5K_AMB
+@@ -632,7 +632,7 @@ config SENSORS_I5K_AMB
config SENSORS_SPARX5
tristate "Sparx5 SoC temperature sensor"
writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
host->ioaddr + SDHCI_PRESET_FOR_SDR104);
preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
-@@ -425,8 +437,9 @@ static int sdhci_at91_probe(struct platf
+@@ -413,8 +425,9 @@ static int sdhci_at91_probe(struct platf
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
pm_runtime_use_autosuspend(&pdev->dev);
sdhci_set_uhs_signaling(host, timing);
/* reenable SDCLK */
-@@ -366,6 +383,20 @@ static const struct dev_pm_ops sdhci_at9
- NULL)
+@@ -360,6 +377,20 @@ static const struct dev_pm_ops sdhci_at9
+ RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, sdhci_at91_runtime_resume, NULL)
};
+static void at91_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
static int sdhci_at91_probe(struct platform_device *pdev)
{
const struct sdhci_at91_soc_data *soc_data;
-@@ -445,6 +476,8 @@ static int sdhci_at91_probe(struct platf
+@@ -433,6 +464,8 @@ static int sdhci_at91_probe(struct platf
if (ret)
goto pm_runtime_disable;
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
-@@ -417,6 +417,9 @@ static int sdhci_at91_probe(struct platf
+@@ -411,6 +411,9 @@ static int sdhci_at91_probe(struct platf
priv = sdhci_pltfm_priv(pltfm_host);
priv->soc_data = soc_data;
+
priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
if (IS_ERR(priv->mainck)) {
- if (soc_data->baseclk_is_generated_internally) {
+ if (soc_data->baseclk_is_generated_internally)
--- a/drivers/mmc/host/sdhci-of-at91.c
+++ b/drivers/mmc/host/sdhci-of-at91.c
-@@ -419,6 +419,8 @@ static int sdhci_at91_probe(struct platf
+@@ -413,6 +413,8 @@ static int sdhci_at91_probe(struct platf
/* Perform a software reset before using the IP */
sdhci_at91_reset(host, SDHCI_RESET_ALL);
};
static const struct sdhci_at91_soc_data soc_data_sama7g5 = {
-@@ -336,9 +339,11 @@ static int sdhci_at91_runtime_suspend(st
+@@ -332,9 +335,11 @@ static int sdhci_at91_runtime_suspend(st
if (host->tuning_mode != SDHCI_TUNING_MODE_3)
mmc_retune_needed(host->mmc);
+ clk_disable_unprepare(priv->mainck);
+ }
- return ret;
+ return 0;
}
-@@ -359,6 +364,9 @@ static int sdhci_at91_runtime_resume(str
+@@ -355,6 +360,9 @@ static int sdhci_at91_runtime_resume(str
goto out;
}
};
static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
-@@ -506,9 +506,7 @@ static int sdhci_at91_probe(struct platf
+@@ -494,9 +494,7 @@ static int sdhci_at91_probe(struct platf
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
pm_runtime_use_autosuspend(&pdev->dev);
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
-@@ -270,6 +270,7 @@
+@@ -317,6 +317,7 @@
#define SDHCI_PRESET_FOR_SDR104 0x6C
#define SDHCI_PRESET_FOR_DDR50 0x6E
#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
+#define SDHCI_PRESET_FOR_HS400_AT91 0x244 /* AT91 specific */
- #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)
- #define SDHCI_PRESET_CLKGEN_SEL BIT(10)
- #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)
-@@ -484,6 +485,10 @@ struct sdhci_host {
+
+ /* UHS2 */
+ #define SDHCI_PRESET_FOR_UHS2 0x74
+@@ -536,6 +537,10 @@ struct sdhci_host {
#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
/* Issue CMD and DATA reset together */
#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
-@@ -147,7 +147,7 @@ config SPI_AT91_USART
+@@ -180,7 +180,7 @@ config SPI_AT91_USART
config SPI_ATMEL_QUADSPI
tristate "Atmel Quad SPI Controller"
This enables support for the Quad SPI controller in master mode.
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
-@@ -1053,9 +1053,9 @@ static int atmel_qspi_set_pad_calibratio
+@@ -1052,9 +1052,9 @@ static int atmel_qspi_set_pad_calibratio
ATMEL_QSPI_TIMEOUT);
/* Refresh analogic blocks every 1 ms.*/
return ret;
}
-@@ -1114,7 +1114,7 @@ static int atmel_qspi_sama7g5_init(struc
+@@ -1113,7 +1113,7 @@ static int atmel_qspi_sama7g5_init(struc
* Check if the SoC supports pad calibration in Octal SPI mode.
* Proceed only if both the capabilities are true.
*/
ret = atmel_qspi_set_pad_calibration(aq);
if (ret)
return ret;
-@@ -1649,6 +1649,17 @@ static const struct atmel_qspi_caps atme
+@@ -1672,6 +1672,17 @@ static const struct atmel_qspi_caps atme
.has_dllon = true,
};
static const struct of_device_id atmel_qspi_dt_ids[] = {
{
.compatible = "atmel,sama5d2-qspi",
-@@ -1678,6 +1689,10 @@ static const struct of_device_id atmel_q
+@@ -1701,6 +1712,10 @@ static const struct of_device_id atmel_q
.compatible = "microchip,sama7d65-qspi",
.data = &atmel_sama7d65_qspi_caps,
},
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
-@@ -127,7 +127,7 @@ config NVMEM_JZ4780_EFUSE
+@@ -150,7 +150,7 @@ config NVMEM_JZ4780_EFUSE
config NVMEM_LAN9662_OTPC
tristate "Microchip LAN9662 OTP controller support"
+}
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
-@@ -1108,6 +1108,8 @@ static const struct sparx5_ops sparx5_op
+@@ -1107,6 +1107,8 @@ static const struct sparx5_ops sparx5_op
.fdma_deinit = &sparx5_fdma_deinit,
.fdma_poll = &sparx5_fdma_napi_callback,
.fdma_xmit = &sparx5_fdma_xmit,