]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915: Extract display registers from i915_reg.h to display
authorUma Shankar <uma.shankar@intel.com>
Thu, 5 Feb 2026 09:43:22 +0000 (15:13 +0530)
committerUma Shankar <uma.shankar@intel.com>
Thu, 12 Feb 2026 10:00:36 +0000 (15:30 +0530)
There are certain register definitions which are defined in i915_reg.h
which are exclusively needed by display. Move the same to display
headers to remove i915_reg.h includes from display. This is a step
towards making display independent of i915.

intel_clock_gating.c can include display header directly, since its
usage is planned to be re-factored and will be moved within display.

v3: Updated subject and commit message (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-2-uma.shankar@intel.com
drivers/gpu/drm/i915/display/intel_display_regs.h
drivers/gpu/drm/i915/display/intel_pch_display.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_clock_gating.c

index 9740f32ced24941f2a82b9d8d8fa949bcd340699..a9bbd20c27ec7b3be5ffa4e549264cdcbe3eab38 100644 (file)
 #define  TRANS_BPC_6                   REG_FIELD_PREP(TRANS_BPC_MASK, 2)
 #define  TRANS_BPC_12                  REG_FIELD_PREP(TRANS_BPC_MASK, 3)
 
+#define _TRANSA_CHICKEN2       0xf0064
+#define _TRANSB_CHICKEN2       0xf1064
+#define TRANS_CHICKEN2(pipe)   _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_CHICKEN2_TIMING_OVERRIDE               REG_BIT(31)
+#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED         REG_BIT(29)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK                REG_GENMASK(28, 27)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)          REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER    REG_BIT(26)
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
+
 #define PCH_DP_B               _MMIO(0xe4100)
 #define PCH_DP_C               _MMIO(0xe4200)
 #define PCH_DP_D               _MMIO(0xe4300)
index 16619f7be5f86cae573b56bc43c8e1934172d6fc..69c7952a14136438ba42ffada5eb64475591d954 100644 (file)
@@ -6,7 +6,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_crt.h"
 #include "intel_crt_regs.h"
 #include "intel_de.h"
index f928db78a3fa5601353dcc3e67881644c8bf2568..f65f50bf44ba68152366c3b20d6403196273f713 100644 (file)
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE   REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE    REG_BIT(4)
 
-#define _TRANSA_CHICKEN2        0xf0064
-#define _TRANSB_CHICKEN2        0xf1064
-#define TRANS_CHICKEN2(pipe)   _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define   TRANS_CHICKEN2_TIMING_OVERRIDE               REG_BIT(31)
-#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED         REG_BIT(29)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK                REG_GENMASK(28, 27)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)          REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER    REG_BIT(26)
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
-
 #define SOUTH_CHICKEN1         _MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR     19
 #define  FDIA_PHASE_SYNC_SHIFT_EN      18
index 7336934bb9345fc9cb9cd28ee41de18151aa3562..4e18d5a22112f82c6764457d62841b26fa175205 100644 (file)
@@ -30,7 +30,7 @@
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
 #include "display/intel_display_core.h"
-
+#include "display/intel_display_regs.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"