drm/amd/display: Pass min page size from SOC BB to dml2_1 plane config

[Why]
Like dml2_0 this isn't guaranteed to be constant for every ASIC.

This can cause corruption or underflow for linear surfaces due to a
wrong PTE_ROW_HEIGHT_LINEAR value if not correctly specified.

[How]
Like dml2_0 pass in the SOC bb into the plane configuration population
functions.

Set both GPUVM and HostVM page sizes in the overrides.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
index 5d7b6c3994704ccc26ff367033f46f6bd9e7fc92..476030193f14991a0b893851499c69d22065b6fe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
@@ -389,7 +389,9 @@ static void populate_dml21_dummy_surface_cfg(struct dml2_surface_cfg *surface, c
        surface->tiling = dml2_sw_64kb_2d;
 }
 
-static void populate_dml21_dummy_plane_cfg(struct dml2_plane_parameters *plane, const struct dc_stream_state *stream)
+static void populate_dml21_dummy_plane_cfg(struct dml2_plane_parameters *plane,
+                                          const struct dc_stream_state *stream,
+                                          const struct dml2_soc_bb *soc_bb)
 {
        unsigned int width, height;
 
@@ -433,7 +435,8 @@ static void populate_dml21_dummy_plane_cfg(struct dml2_plane_parameters *plane,
        plane->pixel_format = dml2_444_32;
 
        plane->dynamic_meta_data.enable = false;
-       plane->overrides.gpuvm_min_page_size_kbytes = 256;
+       plane->overrides.gpuvm_min_page_size_kbytes = soc_bb->gpuvm_min_page_size_kbytes;
+       plane->overrides.hostvm_min_page_size_kbytes = soc_bb->hostvm_min_page_size_kbytes;
 }
 
 static void populate_dml21_surface_config_from_plane_state(
@@ -504,7 +507,7 @@ static const struct scaler_data *get_scaler_data_for_plane(
 
 static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dml_ctx,
                struct dml2_plane_parameters *plane, const struct dc_plane_state *plane_state,
-               const struct dc_state *context, unsigned int stream_index)
+               const struct dc_state *context, unsigned int stream_index, const struct dml2_soc_bb *soc_bb)
 {
        const struct scaler_data *scaler_data = get_scaler_data_for_plane(dml_ctx, plane_state, context);
        struct dc_stream_state *stream = context->streams[stream_index];
@@ -648,7 +651,8 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm
        plane->composition.rotation_angle = (enum dml2_rotation_angle) plane_state->rotation;
        plane->stream_index = stream_index;
 
-       plane->overrides.gpuvm_min_page_size_kbytes = 256;
+       plane->overrides.gpuvm_min_page_size_kbytes = soc_bb->gpuvm_min_page_size_kbytes;
+       plane->overrides.hostvm_min_page_size_kbytes = soc_bb->hostvm_min_page_size_kbytes;
 
        plane->immediate_flip = plane_state->flip_immediate;
 
@@ -786,7 +790,9 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
                if (context->stream_status[stream_index].plane_count == 0) {
                        disp_cfg_plane_location = dml_dispcfg->num_planes++;
                        populate_dml21_dummy_surface_cfg(&dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->streams[stream_index]);
-                       populate_dml21_dummy_plane_cfg(&dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->streams[stream_index]);
+                       populate_dml21_dummy_plane_cfg(
+                               &dml_dispcfg->plane_descriptors[disp_cfg_plane_location],
+                               context->streams[stream_index], &dml_ctx->v21.dml_init.soc_bb);
                        dml_dispcfg->plane_descriptors[disp_cfg_plane_location].stream_index = disp_cfg_stream_location;
                } else {
                        for (plane_index = 0; plane_index < context->stream_status[stream_index].plane_count; plane_index++) {
@@ -798,7 +804,10 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
                                ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
 
                                populate_dml21_surface_config_from_plane_state(in_dc, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].plane_states[plane_index]);
-                               populate_dml21_plane_config_from_plane_state(dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].plane_states[plane_index], context, stream_index);
+                               populate_dml21_plane_config_from_plane_state(
+                                       dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location],
+                                       context->stream_status[stream_index].plane_states[plane_index],
+                                       context, stream_index, &dml_ctx->v21.dml_init.soc_bb);
                                dml_dispcfg->plane_descriptors[disp_cfg_plane_location].stream_index = disp_cfg_stream_location;
 
                                if (dml21_wrapper_get_plane_id(context, context->streams[stream_index]->stream_id, context->stream_status[stream_index].plane_states[plane_index], &dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))