arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading

Add CMA (Contiguous Memory Allocator) reserved-memory regions to all
Xilinx arm64 board device trees to support runtime FPGA programming.

The CMA pool uses dynamic allocation constrained to the low 2 GB DDR region
via alloc-ranges so that the kernel places it within the 32-bit addressable
space.

CMA sizes are chosen per silicon family to accommodate the maximum PL
bitstream/PDI size:
  - Kria K24 SOM:                           64 MB
  - ZynqMP boards:                         128 MB

For Kria K24 SOM the CMA inherited from K26 is overridden to 64 MB.
For Kria SOMs, the CMA node is added to the SOM DTS only, not to
carrier board overlays.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/837e21582e886f1be9f95901109745ac5a8b2a25.1780991287.git.michal.simek@amd.com

diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts
index 653bd9362264e8f3a968386e1a202c9d73af11c7..34ee6af801deeddfacbc04103946a77c7dba1f1a 100644 (file)
--- a/arch/arm/dts/zynqmp-sm-k24-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP SM-K24 RevA
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022-2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -21,3 +21,8 @@
                reg = <0 0 0 0x80000000>;
        };
 };
+
+&cma {
+       size = <0x0 0x4000000>;
+       alignment = <0x0 0x4000000>;
+};

diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 0abec77b3f3ae8ad18eaa4d4db9cd01fa18674c6..c7fe253244f6eab9457ce87f88fcf03a5cb78d42 100644 (file)
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -61,6 +61,15 @@
                        reg = <0x0 0x7ff00000 0x0 0x100000>;
                        no-map;
                };
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
        };
 
        gpio-keys {

diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 34e5b6edab102add6ac7bc349ba6eface34b4b1d..f0e2a0b4588fd4a9bd2c05e9a07975344304b0d3 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -31,6 +31,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &dcc {

diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index 827143377b966a18de815fb3d602d79a0df2d793..e92caefd3aa2eef43559dbcd471bfe6fd0d6d494 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -32,6 +32,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &dcc {

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 33efdbf0e25e07f4a167b9aae90007bb34c84883..2897c423f82eba3dedeec8e7f7f3cc01355fc1da 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
  * (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -41,6 +41,21 @@
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        clock_si5338_0: clk27 { /* u55 SI5338-GM */
                compatible = "fixed-clock";
                #clock-cells = <0>;

diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 13c304520a6029c51a6e82e1c86d360e303a59a3..0b1185d862cd5726734f145477138412588de557 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
  *
  * (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -39,6 +39,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &can0 {

diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 796669fc92c04b2b865a28ca0dc086cbf2a10345..bfcc92cedfad3e99c58d26c11c3913a1b86ee670 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -39,6 +39,21 @@
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        clock_si5338_2: clk26 {
                compatible = "fixed-clock";
                #clock-cells = <0>;

diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index cd80aed9a3880664c4341db44fd3f6a7b1cae401..9b59952993f1a8398fb74c35b7146e66be512f26 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -38,6 +38,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &can0 {

diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 53aa3dca1dca270d4a316d6ec06f0c1526b81af9..722b2e833b448b8e21a9bf8380fc926aab95f08d 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -37,6 +37,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &fpd_dma_chan1 {

diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 4ec8a400494e31861ba3745de2d3f45ad867215e..62f94da334db15883ea910fd6eb819f6e627d5a3 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU100 revC
  *
  * (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  * Nathalie Chan King Choy
@@ -47,6 +47,21 @@
                reg = <0x0 0x0 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9590dd1cd92a3553a164db0e51466c1219010738..a0ef866a259ae6ab8b987d4a9955d4802f2d6854 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
  * (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -45,6 +45,21 @@
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;

diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 3fe7cb410bcfb88e37269d990a808e93554f0642..4479ff7351456a03173cf729a53466a6c0f9519d 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU104
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -43,6 +43,21 @@
                reg = <0x0 0x0 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        clock_8t49n287_5: clk125 {
                compatible = "fixed-clock";
                #clock-cells = <0>;

diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 21ce50e1da93bfe2c8a684d6a87e3a9108812350..0caedc40a51908ab08b7454334589183354f9b02 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU104
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -43,6 +43,21 @@
                reg = <0x0 0x0 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        ina226 {
                compatible = "iio-hwmon";
                io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;

diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 0ac1472c55dd9c95af2bb3eb3706d23b948a8f53..c0bc46faee4ecdcfb64dbdae5e01b0bd78018478 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU106
  *
  * (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -45,6 +45,21 @@
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;

diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 7894daeca9433939570ed10c5535b4c9ec6a70e6..f38edd6145f529c911e5973f75f61d15e826805d 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU111
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -45,6 +45,21 @@
                /* Another 4GB connected to PL */
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;

diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index b9d51fadc2ab7021b5a318641b89bf4a86dac655..1a49ae3ba4e44a15345d62b0cabdac69be7dd00e 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -32,6 +32,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &dcc {

diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index f26d9843243b9573b9ce30b4e1184d2d16273905..1b6f7a605d6f55d12014de4387458ec6b8fab85c 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -35,6 +35,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &dcc {

diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index 86a3217f9ab644a25c3c4f87df6c5705aea68182..b2d71f0f4556a89d29e5b3c73313fcaeb0e225a7 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -36,6 +36,21 @@
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
 };
 
 &dcc {

diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 70b1e81e304c05d6d043a36a719b3cfa275b6d03..3c3c94dcadfc9ba3370c087737fa0024a955f130 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -43,6 +43,21 @@
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;

diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index bc0ca24ff050013e167b8707ee5244eb0beea505..b0f0a74f711ef4b64bf999b5c58fababb83f2fb2 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -43,6 +43,21 @@
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;

diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
index 1215babe214611a6dabf7bc3143659044a092d05..c5b70972ef52d7ff40d55a288f08e10d8c0593c7 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu670-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU670 (67DR)
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -46,6 +46,21 @@
                /* Another 4GB connected to PL */
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;

diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
index e91f280e4576ad3988be577073952bc729b21967..cd96a7a0d1360d4bba4dccd3f5cc11f005fd43c4 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu670-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU670 (67DR) revB
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -46,6 +46,21 @@
                /* Another 4GB connected to PL */
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               cma: linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x0 0x8000000>;
+                       alignment = <0x0 0x8000000>;
+                       alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+                       linux,cma-default;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                autorepeat;