]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915: Remove i915_reg.h from intel_display_device.c
authorUma Shankar <uma.shankar@intel.com>
Thu, 5 Feb 2026 09:43:27 +0000 (15:13 +0530)
committerUma Shankar <uma.shankar@intel.com>
Thu, 12 Feb 2026 10:00:44 +0000 (15:30 +0530)
Move GU_CNTL_PROTECTED and GMD_ID_DISPLAY to common header,
this helps intel_display_device.c free from i915_reg.h dependency.

v2: Move GMD_ID_DISPLAY to display header instead of common (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-7-uma.shankar@intel.com
drivers/gpu/drm/i915/display/intel_display_device.c
drivers/gpu/drm/i915/display/intel_display_regs.h
drivers/gpu/drm/i915/i915_reg.h

index 471f236c9ddf81647856d1706d8daf1ee8013c9b..d449528bfc7f5d587cb39289bc987c5497056627 100644 (file)
@@ -10,7 +10,6 @@
 #include <drm/drm_print.h>
 #include <drm/intel/pciids.h>
 
-#include "i915_reg.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_de.h"
 #include "intel_display.h"
@@ -1539,9 +1538,9 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *
                return NULL;
        }
 
-       gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
-       gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
-       gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
+       gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val);
+       gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val);
+       gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val);
 
        for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
                if (gmd_id.ver == gmdid_display_map[i].ver &&
index ab184670c84532bba986af3db8616b89d976c6f4..c598ccb3c78b5515eb39fab1e20b6bfbaf93df95 100644 (file)
@@ -6,6 +6,9 @@
 
 #include "intel_display_reg_defs.h"
 
+#define GU_CNTL_PROTECTED              _MMIO(0x10100C)
+#define   DEPRESENT                    REG_BIT(9)
+
 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
 #define   GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
 #define   XE2LPD_DFSM_DBUF_OVERLAP_DISABLE     (1 << 3)
 
+#define GMD_ID_DISPLAY                         _MMIO(0x510a0)
+#define   GMD_ID_DISPLAY_ARCH_MASK             REG_GENMASK(31, 22)
+#define   GMD_ID_DISPLAY_RELEASE_MASK          REG_GENMASK(21, 14)
+#define   GMD_ID_DISPLAY_STEP                  REG_GENMASK(5, 0)
+
 #define XE2LPD_DE_CAP                  _MMIO(0x41100)
 #define   XE2LPD_DE_CAP_3DLUT_MASK     REG_GENMASK(31, 30)
 #define   XE2LPD_DE_CAP_DSC_MASK       REG_GENMASK(29, 28)
index bb87af7d3c220025d6e6b8e413832c7b0323e36c..90a5c60e76677315f1a78528809dc2a2a9934b24 100644 (file)
  *  #define GEN8_BAR                    _MMIO(0xb888)
  */
 
-#define GU_CNTL_PROTECTED              _MMIO(0x10100C)
-#define   DEPRESENT                    REG_BIT(9)
-
 #define GU_CNTL                                _MMIO(0x101010)
 #define   LMEM_INIT                    REG_BIT(7)
 #define   DRIVERFLR                    REG_BIT(31)
 #define   MASK_WAKEMEM                         REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS                 REG_BIT(7)
 
-#define GMD_ID_DISPLAY                         _MMIO(0x510a0)
 #define   GMD_ID_ARCH_MASK                     REG_GENMASK(31, 22)
 #define   GMD_ID_RELEASE_MASK                  REG_GENMASK(21, 14)
 #define   GMD_ID_STEP                          REG_GENMASK(5, 0)