clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
byte_intf_clk, the rate-change propagates through the divider up to the
parent PLL (byte_clk_src), halving the byte clock rate.

A simiar issue had been also encountered on SM8750.
b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").

Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
so that clk_set_rate() on the divider adjusts only the divider ratio,
leaving the parent PLL untouched.

Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
Signed-off-by: White Lewis <liu224806@gmail.com>
[pengyu: reword]
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303115550.9279-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c
index 5903a759d4af4979843499a45406d0eafc5eb108..e91dfed0f37e9bfeb495f2d0e12845b415956a94 100644 (file)
--- a/drivers/clk/qcom/dispcc-sc8280xp.c
+++ b/drivers/clk/qcom/dispcc-sc8280xp.c
@@ -1160,7 +1160,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = {
                        &disp0_cc_mdss_byte0_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };
@@ -1175,7 +1174,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = {
                        &disp1_cc_mdss_byte0_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };
@@ -1190,7 +1188,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = {
                        &disp0_cc_mdss_byte1_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };
@@ -1205,7 +1202,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = {
                        &disp1_cc_mdss_byte1_clk_src.clkr.hw,
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_regmap_div_ops,
        },
 };