/* Add one byte if we are using a differential + common byte mode */
bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM ||
st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0;
- /* Mulitiply by the number of hardware channels */
+ /* Multiply by the number of hardware channels */
bytes_to_read *= st->chip->num_voltage_inputs;
for (i = 0; i < cnv_nb; i++) {
};
enum ad4170_ref_buf {
- AD4170_REF_BUF_PRE, /* Pre-charge referrence buffer */
- AD4170_REF_BUF_FULL, /* Full referrence buffering */
- AD4170_REF_BUF_BYPASS, /* Bypass referrence buffering */
+ AD4170_REF_BUF_PRE, /* Pre-charge reference buffer */
+ AD4170_REF_BUF_FULL, /* Full reference buffering */
+ AD4170_REF_BUF_BYPASS, /* Bypass reference buffering */
};
/* maps adi,positive/negative-reference-buffer property values to enum */
/*
* Starting with a quite low frequency, to allow oversampling x32,
- * user is then reponsible to adjust the frequency for the specific case.
+ * user is then responsible to adjust the frequency for the specific case.
*/
ret = ad7380_set_sample_freq(st, sample_rate / 32);
if (ret)
vref_mv = ret / 1000;
} else {
- vref_mv = 1170; /* Build-in ref */
+ vref_mv = 1170; /* Built-in ref */
}
st->chip_info =
{
struct ad7887_state *st = iio_priv(indio_dev);
- /* dummy read: restore default CH0 settin */
+ /* dummy read: restore default CH0 settings */
return spi_sync(st->spi, &st->msg[AD7887_CH0]);
}
#define AD7923_PM_MODE_AS (1) /* auto shutdown */
#define AD7923_PM_MODE_FS (2) /* full shutdown */
#define AD7923_PM_MODE_OPS (3) /* normal operation */
-#define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */
+#define AD7923_SEQUENCE_OFF (0) /* no sequence function */
#define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */
#define AD7923_SEQUENCE_ON (3) /* continuous sequence */
#define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */
#define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
+ (((sequence) & 2) << 9))
- /* write sequence fonction */
+ /* write sequence function */
/* left shift for CR : bit 11 transmit in first */
#define AD7923_SHIFT_REGISTER 4
ret = regmap_clear_bits(st->regmap, ADE9000_REG_MASK0, interrupts);
if (ret) {
- dev_err(dev, "Post-disable update maks0 fail\n");
+ dev_err(dev, "Post-disable update mask0 fail\n");
return ret;
}
at91_adc_buffer_postdisable(indio_dev);
/*
- * Do a sofware reset of the ADC before we go to suspend.
+ * Do a software reset of the ADC before we go to suspend.
* this will ensure that all pins are free from being muxed by the ADC
* and can be used by for other devices.
* Otherwise, ADC will hog them and we can't go to suspend mode.
};
/**
- * struct at91_adc_reg_desc - Various informations relative to registers
+ * struct at91_adc_reg_desc - Various information relative to registers
* @channel_base: Base offset for the channel data registers
* @drdy_mask: Mask of the DRDY field in the relevant registers
* (Interruptions registers mostly)
struct iio_trigger **trig;
bool use_external;
u32 vref_mv;
- u32 res; /* resolution used for convertions */
+ u32 res; /* resolution used for conversions */
wait_queue_head_t wq_data_avail;
const struct at91_adc_caps *caps;
* of register writes, then a wait for a completion callback,
* and finally a register read, during which userspace could issue
* another read request. This lock protects a read access from
- * ocurring before another one has finished.
+ * occurring before another one has finished.
*/
struct mutex lock;
};
};
/**
- * struct max1363_chip_info - chip specifc information
+ * struct max1363_chip_info - chip specific information
* @info: iio core function callbacks structure
* @channels: channel specification
* @num_channels: number of channels
* struct mcp3564_state - working data for a ADC device
* @chip_info: chip specific data
* @spi: SPI device structure
- * @vref_mv: voltage reference value in miliVolts
+ * @vref_mv: voltage reference value in millivolts
* @lock: synchronize access to driver's state members
* @dev_addr: hardware device address
* @oversampling: the index inside oversampling list of the ADC
// SPDX-License-Identifier: GPL-2.0-only
/*
- * MEN 16z188 Analog to Digial Converter
+ * MEN 16z188 Analog to Digital Converter
*
* Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
* Author: Johannes Thumshirn <johannes.thumshirn@men.de>
/*
* Because there is actually only one ADC for both channels, we have to
* wait for enough conversions to happen before getting a significant
- * value when changing channels and the values are far appart.
+ * value when changing channels and the values are far apart.
*/
do {
ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
* read access from userspace. Reading a raw value requires a sequence
* of register writes, then a wait for a event and finally a register
* read, during which userspace could issue another read request.
- * This lock protects a read access from ocurring before another one
+ * This lock protects a read access from occurring before another one
* has finished.
*/
struct mutex lock;
/*
* Read available scales for a specific channel
*
- * NOTE: using extended info insted of iio.read_avail() because access to
+ * NOTE: using extended info instead of iio.read_avail() because access to
* current scales must be locked as they depend on shunt resistor which may
* change runtime. Caller of iio.read_avail() would access the table unlocked
* instead.
* of register writes, then a wait for a completion callback,
* and finally a register read, during which userspace could issue
* another read request. This lock protects a read access from
- * ocurring before another one has finished.
+ * occurring before another one has finished.
*
* This is the palmas_gpadc structure to store run-time information
* and pointers for this driver instance.
/*
* The high limit, low limit and last measurement result are each stored in
- * 2 consequtive registers. 4 bits are in the high bits of the first register
+ * 2 consecutive registers. 4 bits are in the high bits of the first register
* and 8 bits in the next register.
*
* These macros return the address of the first reg for the given channel.
if (ret)
return ret;
- /* Enable writing the measured values to the regsters */
+ /* Enable writing the measured values to the registers */
ret = regmap_set_bits(data->map, BD79124_REG_GEN_CFG,
BD79124_MSK_STATS_EN);
if (ret)
* of register writes, then a wait for a completion callback,
* and finally a register read, during which userspace could issue
* another read request. This lock protects a read access from
- * ocurring before another one has finished.
+ * occurring before another one has finished.
*/
struct mutex lock;
u32 current_clk;
if (priv->aclk) {
/*
* Asynchronous clock modes (e.g. ckmode == 0)
- * From spec: PLL output musn't exceed max rate
+ * From spec: PLL output mustn't exceed max rate
*/
rate = clk_get_rate(priv->aclk);
if (!rate) {
/*
* Clear ovr bit to avoid subsequent calls to IRQ handler.
* This requires to stop ADC first. OVR bit state in ISR,
- * is propaged to CSR register by hardware.
+ * is propagated to CSR register by hardware.
*/
adc->cfg->stop_conv(indio_dev);
stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);
* of register writes, then a wait for a completion callback,
* and finally a register read, during which userspace could issue
* another read request. This lock protects a read access from
- * ocurring before another one has finished.
+ * occurring before another one has finished.
*/
struct mutex lock;
};
{5, 11}, /* CHANNEL 15 */
};
-/* Conversion table from -3 to 55 degrees Celcius */
+/* Conversion table from -3 to 55 degrees Celsius */
static int twl4030_therm_tbl[] = {
30800, 29500, 28300, 27100,
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700,
{
/*
* for any prior chosen channel, when the conversion is ready
- * the result is avalable in GPCH0_LSB, GPCH0_MSB.
+ * the result is available in GPCH0_LSB, GPCH0_MSB.
*/
return TWL6032_GPADC_GPCH0_LSB;
projects / thirdparty / kernel / linux.git / commitdiff
