si->clk_cpu = gd->cpu_clk;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- platform_set_mr(si, gd->bd->bi_dram[i].start,
- gd->bd->bi_dram[i].size, MR_ATTR_DRAM);
+ platform_set_mr(si, gd->dram[i].start,
+ gd->dram[i].size, MR_ATTR_DRAM);
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
}
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- mem_map[index].virt = gd->bd->bi_dram[i].start;
- mem_map[index].phys = gd->bd->bi_dram[i].start;
- mem_map[index].size = gd->bd->bi_dram[i].size;
+ mem_map[index].virt = gd->dram[i].start;
+ mem_map[index].phys = gd->dram[i].start;
+ mem_map[index].size = gd->dram[i].size;
mem_map[index].attrs = attrs;
index++;
}
*/
switch (final_map[index].virt) {
case CFG_SYS_FSL_DRAM_BASE1:
- final_map[index].virt = gd->bd->bi_dram[0].start;
- final_map[index].phys = gd->bd->bi_dram[0].start;
- final_map[index].size = gd->bd->bi_dram[0].size;
+ final_map[index].virt = gd->dram[0].start;
+ final_map[index].phys = gd->dram[0].start;
+ final_map[index].size = gd->dram[0].size;
break;
#ifdef CFG_SYS_FSL_DRAM_BASE2
case CFG_SYS_FSL_DRAM_BASE2:
#if (CONFIG_NR_DRAM_BANKS >= 2)
- final_map[index].virt = gd->bd->bi_dram[1].start;
- final_map[index].phys = gd->bd->bi_dram[1].start;
- final_map[index].size = gd->bd->bi_dram[1].size;
+ final_map[index].virt = gd->dram[1].start;
+ final_map[index].phys = gd->dram[1].start;
+ final_map[index].size = gd->dram[1].size;
#else
final_map[index].size = 0;
#endif
#ifdef CFG_SYS_FSL_DRAM_BASE3
case CFG_SYS_FSL_DRAM_BASE3:
#if (CONFIG_NR_DRAM_BANKS >= 3)
- final_map[index].virt = gd->bd->bi_dram[2].start;
- final_map[index].phys = gd->bd->bi_dram[2].start;
- final_map[index].size = gd->bd->bi_dram[2].size;
+ final_map[index].virt = gd->dram[2].start;
+ final_map[index].phys = gd->dram[2].start;
+ final_map[index].size = gd->dram[2].size;
#else
final_map[index].size = 0;
#endif
}
debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
- gd->bd->bi_dram[i].start = res.a1;
- gd->bd->bi_dram[i].size = res.a2;
+ gd->dram[i].start = res.a1;
+ gd->dram[i].size = res.a2;
- dram_size -= gd->bd->bi_dram[i].size;
+ dram_size -= gd->dram[i].size;
i++;
} while (dram_size);
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
- if (gd->bd->bi_dram[2].size >=
- board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[2].start +
- gd->bd->bi_dram[2].size -
- board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ if (gd->dram[2].size >=
+ board_reserve_ram_top(gd->dram[2].size)) {
+ gd->arch.resv_ram = gd->dram[2].start +
+ gd->dram[2].size -
+ board_reserve_ram_top(gd->dram[2].size);
} else
#endif
{
- if (gd->bd->bi_dram[1].size >=
- board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[1].start +
- gd->bd->bi_dram[1].size -
- board_reserve_ram_top(gd->bd->bi_dram[1].size);
- } else if (gd->bd->bi_dram[0].size >
- board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size -
- board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ if (gd->dram[1].size >=
+ board_reserve_ram_top(gd->dram[1].size)) {
+ gd->arch.resv_ram = gd->dram[1].start +
+ gd->dram[1].size -
+ board_reserve_ram_top(gd->dram[1].size);
+ } else if (gd->dram[0].size >
+ board_reserve_ram_top(gd->dram[0].size)) {
+ gd->arch.resv_ram = gd->dram[0].start +
+ gd->dram[0].size -
+ board_reserve_ram_top(gd->dram[0].size);
}
}
#endif /* CONFIG_RESV_RAM */
}
#endif
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
+ gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+ gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
+ gd->dram[1].size = gd->ram_size -
CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
- if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
- gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
+ if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
+ gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
+ gd->dram[2].size = gd->dram[1].size -
CONFIG_SYS_DDR_BLOCK2_SIZE;
- gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
+ gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
}
#endif
} else {
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].size = gd->ram_size;
}
#ifdef CFG_SYS_MEM_RESERVE_SECURE
- if (gd->bd->bi_dram[0].size >
+ if (gd->dram[0].size >
CFG_SYS_MEM_RESERVE_SECURE) {
- gd->bd->bi_dram[0].size -=
+ gd->dram[0].size -=
CFG_SYS_MEM_RESERVE_SECURE;
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size;
+ gd->arch.secure_ram = gd->dram[0].start +
+ gd->dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
}
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
- if (gd->bd->bi_dram[2].size >=
- board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[2].start +
- gd->bd->bi_dram[2].size -
- board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ if (gd->dram[2].size >=
+ board_reserve_ram_top(gd->dram[2].size)) {
+ gd->arch.resv_ram = gd->dram[2].start +
+ gd->dram[2].size -
+ board_reserve_ram_top(gd->dram[2].size);
} else
#endif
{
- if (gd->bd->bi_dram[1].size >=
- board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[1].start +
- gd->bd->bi_dram[1].size -
- board_reserve_ram_top(gd->bd->bi_dram[1].size);
- } else if (gd->bd->bi_dram[0].size >
- board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size -
- board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ if (gd->dram[1].size >=
+ board_reserve_ram_top(gd->dram[1].size)) {
+ gd->arch.resv_ram = gd->dram[1].start +
+ gd->dram[1].size -
+ board_reserve_ram_top(gd->dram[1].size);
+ } else if (gd->dram[0].size >
+ board_reserve_ram_top(gd->dram[0].size)) {
+ gd->arch.resv_ram = gd->dram[0].start +
+ gd->dram[0].size -
+ board_reserve_ram_top(gd->dram[0].size);
}
}
#endif /* CONFIG_RESV_RAM */
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
+ gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->dram[2].size = dp_ddr_size;
} else {
puts("Not detected");
}
if (i == 2)
continue; /* skip DP-DDR */
#endif
- ram_start = gd->bd->bi_dram[i].start;
- ram_size = gd->bd->bi_dram[i].size;
+ ram_start = gd->dram[i].start;
+ ram_size = gd->dram[i].size;
#ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram >= ram_start &&
gd->arch.resv_ram < ram_start + ram_size)
{
__maybe_unused int ret = 0;
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)
- struct bd_info *bd = gd->bd;
int bank;
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start[bank] = bd->bi_dram[bank].start;
- size[bank] = bd->bi_dram[bank].size;
+ start[bank] = gd->dram[bank].start;
+ size[bank] = gd->dram[bank].size;
#ifdef CONFIG_ARMV7_NONSEC
ret = armv7_apply_memory_carveout(&start[bank], &size[bank]);
if (ret)
params->hdr.tag = ATAG_MEM;
params->hdr.size = tag_size (tag_mem32);
- params->u.mem.start = bd->bi_dram[i].start;
- params->u.mem.size = bd->bi_dram[i].size;
+ params->u.mem.start = gd->dram[i].start;
+ params->u.mem.size = gd->dram[i].size;
params = tag_next (params);
}
__weak void dram_bank_mmu_setup(int bank)
{
- struct bd_info *bd = gd->bd;
int i;
- /* bd->bi_dram is available only after relocation */
+ /* gd->dram is available only after relocation */
if ((gd->flags & GD_FLG_RELOC) == 0)
return;
debug("%s: bank: %d\n", __func__, bank);
- for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
- i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
- (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
+ for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT;
+ i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) +
+ (gd->dram[bank].size >> MMU_SECTION_SHIFT);
i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3)))
dst = image - text_offset;
else
- dst = gd->bd->bi_dram[0].start;
+ dst = gd->dram[0].start;
*relocated_addr = ALIGN(dst, SZ_2M) + text_offset;
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = get_effective_memsize();
+ gd->dram[0].start = gd->ram_base;
+ gd->dram[0].size = get_effective_memsize();
if (gd->ram_size > SZ_2G) {
- gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G;
- gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+ gd->dram[1].start = gd->ram_base + SZ_2G;
+ gd->dram[1].size = gd->ram_size - SZ_2G;
}
return 0;
;
/* Align RAM mapping to page boundaries */
- base = gd->bd->bi_dram[0].start;
- size = gd->bd->bi_dram[0].size;
+ base = gd->dram[0].start;
+ size = gd->dram[0].size;
size += (base - ALIGN_DOWN(base, SZ_4K));
base = ALIGN_DOWN(base, SZ_4K);
size = ALIGN(size, SZ_4K);
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
static inline bool check_in_dram(ulong addr)
{
int i;
- struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
- if (bd->bi_dram[i].size) {
- if (addr >= bd->bi_dram[i].start &&
- addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ if (gd->dram[i].size) {
+ if (addr >= gd->dram[i].start &&
+ addr < (gd->dram[i].start + gd->dram[i].size))
return true;
}
}
static inline bool check_in_dram(ulong addr)
{
int i;
- struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
- if (bd->bi_dram[i].size) {
- if (addr >= bd->bi_dram[i].start &&
- addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ if (gd->dram[i].size) {
+ if (addr >= gd->dram[i].start &&
+ addr < (gd->dram[i].start + gd->dram[i].size))
return true;
}
}
phys_size_t size;
while (current_bank > 0) {
- if (gd->bd->bi_dram[current_bank - 1].start >
- gd->bd->bi_dram[current_bank].start) {
- start = gd->bd->bi_dram[current_bank - 1].start;
- size = gd->bd->bi_dram[current_bank - 1].size;
-
- gd->bd->bi_dram[current_bank - 1].start =
- gd->bd->bi_dram[current_bank].start;
- gd->bd->bi_dram[current_bank - 1].size =
- gd->bd->bi_dram[current_bank].size;
-
- gd->bd->bi_dram[current_bank].start = start;
- gd->bd->bi_dram[current_bank].size = size;
+ if (gd->dram[current_bank - 1].start >
+ gd->dram[current_bank].start) {
+ start = gd->dram[current_bank - 1].start;
+ size = gd->dram[current_bank - 1].size;
+
+ gd->dram[current_bank - 1].start =
+ gd->dram[current_bank].start;
+ gd->dram[current_bank - 1].size =
+ gd->dram[current_bank].size;
+
+ gd->dram[current_bank].start = start;
+ gd->dram[current_bank].size = size;
}
current_bank--;
}
continue;
if (start >= phys_sdram_1_start && start <= end1) {
- gd->bd->bi_dram[i].start = start;
+ gd->dram[i].start = start;
if ((end + 1) <= end1)
- gd->bd->bi_dram[i].size =
+ gd->dram[i].size =
end - start + 1;
else
- gd->bd->bi_dram[i].size = end1 - start;
+ gd->dram[i].size = end1 - start;
dram_bank_sort(i);
i++;
} else if (start >= phys_sdram_2_start && start <= end2) {
- gd->bd->bi_dram[i].start = start;
+ gd->dram[i].start = start;
if ((end + 1) <= end2)
- gd->bd->bi_dram[i].size =
+ gd->dram[i].size =
end - start + 1;
else
- gd->bd->bi_dram[i].size = end2 - start;
+ gd->dram[i].size = end2 - start;
dram_bank_sort(i);
i++;
/* If error, set to the default value */
if (!i) {
- gd->bd->bi_dram[0].start = phys_sdram_1_start;
- gd->bd->bi_dram[0].size = phys_sdram_1_size;
- gd->bd->bi_dram[1].start = phys_sdram_2_start;
- gd->bd->bi_dram[1].size = phys_sdram_2_size;
+ gd->dram[0].start = phys_sdram_1_start;
+ gd->dram[0].size = phys_sdram_1_size;
+ gd->dram[1].start = phys_sdram_2_start;
+ gd->dram[1].size = phys_sdram_2_size;
}
return 0;
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
- if (gd->bd->bi_dram[i].start == 0)
+ if (gd->dram[i].start == 0)
break;
- imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
- imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
- imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx8m_mem_map[entry].phys = gd->dram[i].start;
+ imx8m_mem_map[entry].virt = gd->dram[i].start;
+ imx8m_mem_map[entry].size = gd->dram[i].size;
imx8m_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
sdram_b2_size = 0;
}
- gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+ gd->dram[bank].start = PHYS_SDRAM;
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
- gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
- gd->bd->bi_dram[bank].start = optee_start + optee_size;
- gd->bd->bi_dram[bank].size = PHYS_SDRAM +
- sdram_b1_size - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].start = optee_start + optee_size;
+ gd->dram[bank].size = PHYS_SDRAM +
+ sdram_b1_size - gd->dram[bank].start;
}
} else {
- gd->bd->bi_dram[bank].size = sdram_b1_size;
+ gd->dram[bank].size = sdram_b1_size;
}
if (sdram_b2_size) {
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
- gd->bd->bi_dram[bank].start = 0x100000000UL;
- gd->bd->bi_dram[bank].size = sdram_b2_size;
+ gd->dram[bank].start = 0x100000000UL;
+ gd->dram[bank].size = sdram_b2_size;
}
return 0;
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
- if (gd->bd->bi_dram[i].start == 0)
+ if (gd->dram[i].start == 0)
break;
- imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
- imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
- imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start;
+ imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start;
+ imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size;
imx8ulp_arm64_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
if (ret)
return ret;
- gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+ gd->dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
- gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
- gd->bd->bi_dram[bank].start = optee_start + optee_size;
- gd->bd->bi_dram[bank].size = PHYS_SDRAM +
- sdram_size - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].start = optee_start + optee_size;
+ gd->dram[bank].size = PHYS_SDRAM +
+ sdram_size - gd->dram[bank].start;
}
} else {
- gd->bd->bi_dram[bank].size = sdram_size;
+ gd->dram[bank].size = sdram_size;
}
return 0;
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx9_mem_map)) {
- if (gd->bd->bi_dram[i].start == 0)
+ if (gd->dram[i].start == 0)
break;
- imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start;
- imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start;
- imx9_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx9_mem_map[entry].phys = gd->dram[i].start;
+ imx9_mem_map[entry].virt = gd->dram[i].start;
+ imx9_mem_map[entry].size = gd->dram[i].size;
imx9_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx9_mem_map[entry].phys, imx9_mem_map[entry].size);
sdram_b2_size = 0;
}
- gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+ gd->dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
- gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
- gd->bd->bi_dram[bank].start = optee_start + optee_size;
- gd->bd->bi_dram[bank].size = PHYS_SDRAM +
- sdram_b1_size - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].start = optee_start + optee_size;
+ gd->dram[bank].size = PHYS_SDRAM +
+ sdram_b1_size - gd->dram[bank].start;
}
} else {
- gd->bd->bi_dram[bank].size = sdram_b1_size;
+ gd->dram[bank].size = sdram_b1_size;
}
if (sdram_b2_size) {
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
- gd->bd->bi_dram[bank].start = 0x100000000UL;
- gd->bd->bi_dram[bank].size = sdram_b2_size;
+ gd->dram[bank].start = 0x100000000UL;
+ gd->dram[bank].size = sdram_b2_size;
}
return 0;
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx93_mem_map)) {
- if (gd->bd->bi_dram[i].start == 0)
+ if (gd->dram[i].start == 0)
break;
- imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start;
- imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start;
- imx93_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx93_mem_map[entry].phys = gd->dram[i].start;
+ imx93_mem_map[entry].virt = gd->dram[i].start;
+ imx93_mem_map[entry].size = gd->dram[i].size;
imx93_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx93_mem_map[entry].phys, imx93_mem_map[entry].size);
sdram_b2_size = 0;
}
- gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+ gd->dram[bank].start = PHYS_SDRAM;
if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
- gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
- gd->bd->bi_dram[bank].start = optee_start + optee_size;
- gd->bd->bi_dram[bank].size = PHYS_SDRAM +
- sdram_b1_size - gd->bd->bi_dram[bank].start;
+ gd->dram[bank].start = optee_start + optee_size;
+ gd->dram[bank].size = PHYS_SDRAM +
+ sdram_b1_size - gd->dram[bank].start;
}
} else {
- gd->bd->bi_dram[bank].size = sdram_b1_size;
+ gd->dram[bank].size = sdram_b1_size;
}
if (sdram_b2_size) {
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
- gd->bd->bi_dram[bank].start = 0x100000000UL;
- gd->bd->bi_dram[bank].size = sdram_b2_size;
+ gd->dram[bank].start = 0x100000000UL;
+ gd->dram[bank].size = sdram_b2_size;
}
return 0;
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+ gd->dram[1].start = PHYS_SDRAM_2;
+ gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
return 0;
}
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = imx_ddr_size();
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = imx_ddr_size();
return 0;
}
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start[bank] = gd->bd->bi_dram[bank].start;
- size[bank] = gd->bd->bi_dram[bank].size;
+ start[bank] = gd->dram[bank].start;
+ size[bank] = gd->dram[bank].size;
}
ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
/*
* Config single DRAM bank
*/
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
* build_mem_map.
*/
if (last_end == dram_wins[win].base) {
- gd->bd->bi_dram[bank - 1].size += size;
+ gd->dram[bank - 1].size += size;
last_end += size;
} else {
if (bank == CONFIG_NR_DRAM_BANKS) {
return -ENOBUFS;
}
- gd->bd->bi_dram[bank].start = dram_wins[win].base;
- gd->bd->bi_dram[bank].size = size;
+ gd->dram[bank].start = dram_wins[win].base;
+ gd->dram[bank].size = size;
last_end = dram_wins[win].base + size;
++bank;
}
* the rest with zeros.
*/
for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
- gd->bd->bi_dram[bank].start = 0;
- gd->bd->bi_dram[bank].size = 0;
+ gd->dram[bank].start = 0;
+ gd->dram[bank].size = 0;
}
return 0;
*/
phys_size_t max_bank0_size = SZ_4G - SZ_1G;
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size <= max_bank0_size) {
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
- gd->bd->bi_dram[0].size = max_bank0_size;
+ gd->dram[0].size = max_bank0_size;
if (CONFIG_NR_DRAM_BANKS > 1) {
- gd->bd->bi_dram[1].start = SZ_4G;
- gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
+ gd->dram[1].start = SZ_4G;
+ gd->dram[1].size = gd->ram_size - max_bank0_size;
}
return 0;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
- gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
+ gd->dram[i].start = mvebu_sdram_bar(i);
+ gd->dram[i].size = mvebu_sdram_bs(i);
/* Clip the banksize to 1GiB if it exceeds the max size */
- size += gd->bd->bi_dram[i].size;
+ size += gd->dram[i].size;
if (size > MVEBU_SDRAM_SIZE_MAX)
mvebu_sdram_bs_set(i, 0x40000000);
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
void dram_bank_mmu_setup(int bank)
{
- struct bd_info *bd = gd->bd;
int i;
- u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
- u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+ u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT;
+ u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT;
u32 end = start + size;
debug("%s: bank: %d\n", __func__, bank);
size0 = get_sdr_cs_size(CS0);
size1 = get_sdr_cs_size(CS1);
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = size0;
+ gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+ gd->dram[1].size = size1;
return 0;
}
size0 = get_sdr_cs_size(CS0);
size1 = get_sdr_cs_size(CS1);
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = size0;
+ gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+ gd->dram[1].size = size1;
return 0;
}
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
/* Generate entires for DRAM in 32bit address space */
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start = gd->bd->bi_dram[bank].start;
- size = gd->bd->bi_dram[bank].size;
+ start = gd->dram[bank].start;
+ size = gd->dram[bank].size;
/* Skip empty DRAM banks */
if (!size)
/* Generate entires for DRAM in 64bit address space */
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start = gd->bd->bi_dram[bank].start;
- size = gd->bd->bi_dram[bank].size;
+ start = gd->dram[bank].start;
+ size = gd->dram[bank].size;
/* Skip empty DRAM banks */
if (!size)
/* Generate entries for DRAM in 32bit address space */
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start = gd->bd->bi_dram[bank].start;
- size = gd->bd->bi_dram[bank].size;
+ start = gd->dram[bank].start;
+ size = gd->dram[bank].size;
/* Skip empty DRAM banks */
if (!size)
int rockchip_dram_init_banksize_fixup(struct bd_info *bd)
{
- size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size;
+ size_t ram_top = gd->dram[1].start + gd->dram[1].size;
if (ram_top > DRAM_GAP_START) {
- bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start;
+ gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start;
if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) {
- bd->bi_dram[2].start = DRAM_GAP_END;
- bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start;
+ gd->dram[2].start = DRAM_GAP_END;
+ gd->dram[2].size = ram_top - gd->dram[2].start;
}
}
/*
* Rockchip guaranteed DDR_MEM is ordered so no need to worry about
- * bi_dram order.
+ * dram order.
*/
for (i = 0, j = 0; i < ddr_info->count; i++, j++) {
phys_size_t size = ddr_info->bank[(i + ddr_info->count)];
* split the region in two, one for before the
* reserved memory area and one for after.
*/
- gd->bd->bi_dram[j].start = start_addr;
- gd->bd->bi_dram[j].size = rsrv_start - start_addr;
+ gd->dram[j].start = start_addr;
+ gd->dram[j].size = rsrv_start - start_addr;
j++;
return -ENOMEM;
}
- gd->bd->bi_dram[j].start = start_addr;
- gd->bd->bi_dram[j].size = size;
+ gd->dram[j].start = start_addr;
+ gd->dram[j].size = size;
}
return 0;
ret);
/* Reserve 2M for ATF bl31 */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
- gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
+ gd->dram[0].size = top - gd->dram[0].start;
/* Add usable memory beyond the blob of space for peripheral near 4GB */
if (ram_top > SZ_4G && top < SZ_4G) {
- gd->bd->bi_dram[1].start = SZ_4G;
- gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
+ gd->dram[1].start = SZ_4G;
+ gd->dram[1].size = ram_top - gd->dram[1].start;
} else if (ram_top > SZ_4G && top == SZ_4G) {
- gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
+ gd->dram[0].size = ram_top - gd->dram[0].start;
}
#else
#ifdef CONFIG_SPL_OPTEE_IMAGE
TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) {
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = tos_parameter->tee_mem.phy_addr
- CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+ gd->dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
- gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
+ gd->dram[1].size = top - gd->dram[1].start;
} else {
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x8400000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
- + gd->bd->bi_dram[0].size + 0x2000000;
- gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
+ gd->dram[1].start = CFG_SYS_SDRAM_BASE
+ + gd->dram[0].size + 0x2000000;
+ gd->dram[1].size = top - gd->dram[1].start;
}
#else
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = top - gd->dram[0].start;
#endif
#endif
}
/* This has to be done post-relocation since gd->bd isn't preserved */
-static void qcom_configure_bi_dram(void)
+static void qcom_configure_dram(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start;
- gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size;
+ gd->dram[i].start = prevbl_ddr_banks[i].start;
+ gd->dram[i].size = prevbl_ddr_banks[i].size;
}
}
int dram_init_banksize(void)
{
- qcom_configure_bi_dram();
+ qcom_configure_dram();
return 0;
}
*/
mem_map[0].phys = 0x1000;
mem_map[0].virt = mem_map[0].phys;
- mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
+ mem_map[0].size = gd->dram[0].start - mem_map[0].phys;
mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN;
- for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) {
- mem_map[i].phys = gd->bd->bi_dram[j].start;
+ for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) {
+ mem_map[i].phys = gd->dram[j].start;
mem_map[i].virt = mem_map[i].phys;
- mem_map[i].size = gd->bd->bi_dram[j].size;
+ mem_map[i].size = gd->dram[j].size;
mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
PTE_BLOCK_INNER_SHARE;
}
void lmb_arch_add_memory(void)
{
int i;
- struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- if (bd->bi_dram[i].size)
- lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size);
+ if (gd->dram[i].size)
+ lmb_add(gd->dram[i].start, gd->dram[i].size);
}
}
#endif
void dram_bank_mmu_setup(int bank)
{
- struct bd_info *bd = gd->bd;
u32 start, size;
int i;
* The default implementation of this function allows the DRAM dcache
* to be enabled only after relocation. However, to speed up ECC
* initialization, we want to be able to enable DRAM dcache before
- * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+ * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram
* is set first).
*/
- start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
- size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+ start = gd->dram[bank].start >> MMU_SECTION_SHIFT;
+ size = gd->dram[bank].size >> MMU_SECTION_SHIFT;
for (i = start; i < start + size; i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
dev->mtd = mtd;
break;
case STM32PROG_RAM:
- first_addr = gd->bd->bi_dram[0].start;
- last_addr = first_addr + gd->bd->bi_dram[0].size;
+ first_addr = gd->dram[0].start;
+ last_addr = first_addr + gd->dram[0].size;
dev->erase_size = 1;
break;
default:
*/
void dram_bank_mmu_setup(int bank)
{
- struct bd_info *bd = gd->bd;
int i;
phys_addr_t start;
phys_addr_t addr;
size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
#endif
} else if (gd->flags & GD_FLG_RELOC) {
- /* bd->bi_dram is available only after relocation */
- start = bd->bi_dram[bank].start;
- size = bd->bi_dram[bank].size;
+ /* gd->dram is available only after relocation */
+ start = gd->dram[bank].start;
+ size = gd->dram[bank].size;
use_lmb = true;
} else {
/* mark cacheable and executable the beggining of the DDR */
/* fall back to default DRAM bank size computation */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PHYS_64BIT
if (gd->ram_size > SZ_2G) {
- gd->bd->bi_dram[1].start = 0x100000000;
- gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+ gd->dram[1].start = 0x100000000;
+ gd->dram[1].size = gd->ram_size - SZ_2G;
} else
#endif
{
- gd->bd->bi_dram[1].start = 0;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[1].start = 0;
+ gd->dram[1].size = 0;
}
return 0;
* carve-out, as mentioned above.
*
* This function is called before dram_init_banksize(), so we can't simply
- * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
+ * return gd->dram[1].start + gd->dram[1].size.
*/
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
}
for (i = 0; i < ram_bank_count; i++) {
- gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
- gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
+ gd->dram[i].start = tegra_mem_map[1 + i].virt;
+ gd->dram[i].size = tegra_mem_map[1 + i].size;
}
return 0;
return ret;
for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
- if (i < ARRAY_SIZE(gd->bd->bi_dram)) {
- gd->bd->bi_dram[i].start = dram_map[i].base;
- gd->bd->bi_dram[i].size = dram_map[i].size;
+ if (i < ARRAY_SIZE(gd->dram)) {
+ gd->dram[i].start = dram_map[i].base;
+ gd->dram[i].size = dram_map[i].size;
}
if (!dram_map[i].size)
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
+#include <asm/global_data.h>
#include <fdt_support.h>
#include <fdtdec.h>
#include <jffs2/load_kernel.h>
*/
static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd)
{
+ DECLARE_GLOBAL_DATA_PTR;
unsigned long rsv_addr;
const unsigned long rsv_size = 64;
int i, ret;
uniphier_get_soc_id() != UNIPHIER_LD20_ID)
return 0;
- for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) {
- if (!bd->bi_dram[i].size)
+ for (i = 0; i < ARRAY_SIZE(gd->dram); i++) {
+ if (!gd->dram[i].size)
continue;
- rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size;
+ rsv_addr = gd->dram[i].start + gd->dram[i].size;
rsv_addr -= rsv_size;
ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Zero size means no more DDR that's this is end */
- if (!gd->bd->bi_dram[i].size)
+ if (!gd->dram[i].size)
break;
- versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
- versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
- versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+ versal_mem_map[banks].virt = gd->dram[i].start;
+ versal_mem_map[banks].phys = gd->dram[i].start;
+ versal_mem_map[banks].size = gd->dram[i].size;
versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
banks = banks + 1;
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Zero size means no more DDR that's this is end */
- if (!gd->bd->bi_dram[i].size)
+ if (!gd->dram[i].size)
break;
#if defined(CONFIG_VERSAL_NO_DDR)
- if (gd->bd->bi_dram[i].start < 0x80000000UL ||
- gd->bd->bi_dram[i].start > 0x100000000UL) {
+ if (gd->dram[i].start < 0x80000000UL ||
+ gd->dram[i].start > 0x100000000UL) {
printf("Ignore caches over %llx/%llx\n",
- gd->bd->bi_dram[i].start,
- gd->bd->bi_dram[i].size);
+ gd->dram[i].start,
+ gd->dram[i].size);
continue;
}
#endif
- versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
- versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
- versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+ versal_mem_map[banks].virt = gd->dram[i].start;
+ versal_mem_map[banks].phys = gd->dram[i].start;
+ versal_mem_map[banks].size = gd->dram[i].size;
versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
banks = banks + 1;
* fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info
*
* Transfers DRAM bank information from the global versal2_mem_map[]
- * array to bd->bi_dram[] for passing memory configuration to the
+ * array to gd->dram[] for passing memory configuration to the
* Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical
* address and size are copied.
*
*/
void fill_bd_mem_info(void)
{
- struct bd_info *bd = gd->bd;
int banks = VERSAL2_MEM_MAP_USED;
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
if (!versal2_mem_map[banks].size)
break;
- bd->bi_dram[i].start = versal2_mem_map[banks].phys;
- bd->bi_dram[i].size = versal2_mem_map[banks].size;
+ gd->dram[i].start = versal2_mem_map[banks].phys;
+ gd->dram[i].size = versal2_mem_map[banks].size;
banks++;
}
}
#if !defined(CONFIG_ZYNQMP_NO_DDR)
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Zero size means no more DDR that's this is end */
- if (!gd->bd->bi_dram[i].size)
+ if (!gd->dram[i].size)
break;
- zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
- zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
- zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
+ zynqmp_mem_map[banks].virt = gd->dram[i].start;
+ zynqmp_mem_map[banks].phys = gd->dram[i].start;
+ zynqmp_mem_map[banks].size = gd->dram[i].size;
zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
banks = banks + 1;
* No DDR init yet -> run in L2 cache
*/
gd->ram_size = (4 << 20);
- gd->bd->bi_dram[0].size = gd->ram_size;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[0].size = gd->ram_size;
+ gd->dram[1].size = 0;
}
return 0;
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);
if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) {
- gd->bd->bi_dram[1].start = 0x100000000;
- gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+ gd->dram[1].start = 0x100000000;
+ gd->dram[1].size = gd->ram_size - SZ_2G;
}
return 0;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- start[i] = gd->bd->bi_dram[i].start;
- size[i] = gd->bd->bi_dram[i].size;
+ start[i] = gd->dram[i].start;
+ size[i] = gd->dram[i].size;
}
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
int dram_init_banksize(void)
{
/* These are necessary so TFTP can use LMBs to check its load address */
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = get_effective_memsize();
+ gd->dram[0].start = gd->ram_base;
+ gd->dram[0].size = get_effective_memsize();
return 0;
}
struct memrange *memrange = &lib_sysinfo.memrange[i];
if (memrange->type == CB_MEM_RAM) {
- gd->bd->bi_dram[j].start = memrange->base;
- gd->bd->bi_dram[j].size = memrange->size;
+ gd->dram[j].start = memrange->base;
+ gd->dram[j].size = memrange->size;
j++;
if (j >= CONFIG_NR_DRAM_BANKS)
break;
if (desc->type != EFI_CONVENTIONAL_MEMORY ||
(desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20)
continue;
- gd->bd->bi_dram[num_banks].start = desc->physical_start;
- gd->bd->bi_dram[num_banks].size = desc->num_pages <<
+ gd->dram[num_banks].start = desc->physical_start;
+ gd->dram[num_banks].size = desc->num_pages <<
EFI_PAGE_SHIFT;
num_banks++;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = efi_get_ram_base();
- gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;
+ gd->dram[0].start = efi_get_ram_base();
+ gd->dram[0].size = CONFIG_EFI_RAM_SIZE;
return 0;
}
if (area->start >= 1ULL << 32)
continue;
- gd->bd->bi_dram[num_banks].start = area->start;
- gd->bd->bi_dram[num_banks].size = area->size;
+ gd->dram[num_banks].start = area->start;
+ gd->dram[num_banks].size = area->size;
num_banks++;
}
}
int dram_init(void)
{
gd->ram_size = 1ULL << 31;
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = 0;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
{
u64 high_mem_size;
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = qemu_get_low_memory_size();
+ gd->dram[0].start = 0;
+ gd->dram[0].size = qemu_get_low_memory_size();
high_mem_size = qemu_get_high_memory_size();
if (high_mem_size) {
- gd->bd->bi_dram[1].start = SZ_4G;
- gd->bd->bi_dram[1].size = high_mem_size;
+ gd->dram[1].start = SZ_4G;
+ gd->dram[1].size = high_mem_size;
}
return 0;
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = 0;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
return 0;
/* simply use a single bank to have whole size for now */
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = 0;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
if (mentry->type != SFI_MEM_CONV)
continue;
- gd->bd->bi_dram[bank].start = mentry->phys_start;
- gd->bd->bi_dram[bank].size = mentry->pages << 12;
+ gd->dram[bank].start = mentry->phys_start;
+ gd->dram[bank].size = mentry->pages << 12;
bank++;
}
#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
int arch_fixup_memory_node(void *blob)
{
- struct bd_info *bd = gd->bd;
int bank;
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start[bank] = bd->bi_dram[bank].start;
- size[bank] = bd->bi_dram[bank].size;
+ start[bank] = gd->dram[bank].start;
+ size[bank] = gd->dram[bank].size;
}
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);
if (!ll_boot_init()) {
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = 0;
+ gd->dram[0].size = gd->ram_size;
if (update_mtrr)
mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
mtrr_top = max(mtrr_top,
res_desc->phys_start + res_desc->len);
} else {
- gd->bd->bi_dram[bank].start = res_desc->phys_start;
- gd->bd->bi_dram[bank].size = res_desc->len;
+ gd->dram[bank].start = res_desc->phys_start;
+ gd->dram[bank].size = res_desc->len;
if (update_mtrr)
mtrr_add_request(MTRR_TYPE_WRBACK,
res_desc->phys_start,
res_desc->len);
log_debug("ram %llx %llx\n",
- gd->bd->bi_dram[bank].start,
- gd->bd->bi_dram[bank].size);
+ gd->dram[bank].start,
+ gd->dram[bank].size);
}
}
/* Add the memory below 4GB */
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = low_end;
+ gd->dram[0].start = 0;
+ gd->dram[0].size = low_end;
/*
* Set up an MTRR to the top of low, reserved memory. This is necessary
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
int handoff_arch_save(struct spl_handoff *ho)
{
- ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
+ ho->arch.usable_ram_top = gd->dram[0].size;
ho->arch.hob_list = gd->arch.hob_list;
return 0;
static_assert(CONFIG_NR_DRAM_BANKS >= 3);
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = get_effective_memsize();
- size -= gd->bd->bi_dram[0].size;
+ gd->dram[0].start = gd->ram_base;
+ gd->dram[0].size = get_effective_memsize();
+ size -= gd->dram[0].size;
/* Note: This address space is not mapped via TLB entries in U-Boot */
if (size > 0) {
/* Free space between PCIe bus 3 MEM and NOR */
- gd->bd->bi_dram[1].start = 0xc0200000;
- gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start);
- size -= gd->bd->bi_dram[1].size;
+ gd->dram[1].start = 0xc0200000;
+ gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start);
+ size -= gd->dram[1].size;
}
if (size > 0) {
/* Free space between NOR and NAND */
- gd->bd->bi_dram[2].start = 0xf0000000;
- gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start);
- size -= gd->bd->bi_dram[2].size;
+ gd->dram[2].start = 0xf0000000;
+ gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start);
+ size -= gd->dram[2].size;
}
#else
puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n");
if (!env_get("bootm_low") && !env_get("bootm_size")) {
for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) {
- start[count] = gd->bd->bi_dram[count].start;
- size[count] = gd->bd->bi_dram[count].size;
+ start[count] = gd->dram[count].start;
+ size[count] = gd->dram[count].size;
if (!size[count])
break;
}
size = gd->ram_size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- size -= gd->bd->bi_dram[i].size;
+ size -= gd->dram[i].size;
if (size == 0)
return;
e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3);
- if (e.index < 0 && gd->bd->bi_dram[1].size > 0) {
+ if (e.index < 0 && gd->dram[1].size > 0) {
/*
* If there is no LAW for PCIe 3 MEM then 3rd PCIe controller
* is inactive, which is the case for Turris 1.0 boards. So
printf("Reserving unused ");
print_size(bank_size, "");
printf(" of PCIe 3 MEM for DDR RAM\n");
- gd->bd->bi_dram[1].start -= bank_size;
- gd->bd->bi_dram[1].size += bank_size;
+ gd->dram[1].start -= bank_size;
+ gd->dram[1].size += bank_size;
size -= bank_size;
if (size == 0)
return;
printf("Reserving unused ");
print_size(free_size2, "");
printf(" of PCIe 2 MEM for DDR RAM\n");
- gd->bd->bi_dram[i].start = free_start2;
- gd->bd->bi_dram[i].size = min(size, free_size2);
- size -= gd->bd->bi_dram[i].start;
+ gd->dram[i].start = free_start2;
+ gd->dram[i].size = min(size, free_size2);
+ size -= gd->dram[i].start;
i++;
if (size == 0)
return;
printf("Reserving unused ");
print_size(free_size1, "");
printf(" of PCIe 1 MEM for DDR RAM\n");
- gd->bd->bi_dram[i].start = free_start1;
- gd->bd->bi_dram[i].size = min(size, free_size1);
- size -= gd->bd->bi_dram[i].size;
+ gd->dram[i].start = free_start1;
+ gd->dram[i].size = min(size, free_size1);
+ size -= gd->dram[i].size;
i++;
if (size == 0)
return;
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init (void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
/* We only have one bank of RAM, set it to whatever was detected */
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
* The first node is for I/O device, start from node 1 for
* updating DRAM info.
*/
- mem_map[i + 1].virt = gd->bd->bi_dram[i].start;
- mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
- mem_map[i + 1].size = gd->bd->bi_dram[i].size;
+ mem_map[i + 1].virt = gd->dram[i].start;
+ mem_map[i + 1].phys = gd->dram[i].start;
+ mem_map[i + 1].size = gd->dram[i].size;
mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size =
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size =
get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size =
+ gd->dram[1].start = PHYS_SDRAM_2;
+ gd->dram[1].size =
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
return 0;
dram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
+ dram_size += gd->dram[i].size;
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
board_leds_init();
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
board_leds_init();
int board_init(void)
{
// Address of boot parameters
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
*/
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
- gd->bd->bi_dram[0].size = SZ_16M;
+ gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
+ gd->dram[0].size = SZ_16M;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[1].start = PHYS_SDRAM_2;
switch (gd->ram_size) {
case 0x10000000: /* DDR_16BIT_256MB */
- gd->bd->bi_dram[0].size = 0x10000000;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[0].size = 0x10000000;
+ gd->dram[1].size = 0;
break;
case 0x20000000: /* DDR_32BIT_512MB */
- gd->bd->bi_dram[0].size = 0x20000000;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[0].size = 0x20000000;
+ gd->dram[1].size = 0;
break;
case 0x40000000:
if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
- gd->bd->bi_dram[0].size = 0x20000000;
- gd->bd->bi_dram[1].size = 0x20000000;
+ gd->dram[0].size = 0x20000000;
+ gd->dram[1].size = 0x20000000;
} else { /* DDR_64BIT_1GB */
- gd->bd->bi_dram[0].size = 0x40000000;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[0].size = 0x40000000;
+ gd->dram[1].size = 0;
}
break;
case 0x80000000: /* DDR_64BIT_2GB */
- gd->bd->bi_dram[0].size = 0x40000000;
- gd->bd->bi_dram[1].size = 0x40000000;
+ gd->dram[0].size = 0x40000000;
+ gd->dram[1].size = 0x40000000;
break;
case 0xEFF00000: /* DDR_64BIT_4GB */
- gd->bd->bi_dram[0].size = 0x70000000;
- gd->bd->bi_dram[1].size = 0x7FF00000;
+ gd->dram[0].size = 0x70000000;
+ gd->dram[1].size = 0x7FF00000;
break;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = 0x60000000;
- gd->bd->bi_dram[0].size = 0x8000000;
+ gd->dram[0].start = 0x60000000;
+ gd->dram[0].size = 0x8000000;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ gd->dram[0].start = PHYS_SDRAM;
+ gd->dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
/* set global data memory */
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
/* Number of Row: 14 bits */
if ((reg_val >> 28) == 14)
- gd->bd->bi_dram[0].size -= 0x20000000;
+ gd->dram[0].size -= 0x20000000;
/* Number of Memory Chips */
if ((reg_val & 0x3) > 1) {
- gd->bd->bi_dram[1].start = 0x80000000;
- gd->bd->bi_dram[1].size = 0x40000000;
+ gd->dram[1].start = 0x80000000;
+ gd->dram[1].size = 0x40000000;
}
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = mx53_dram_size[0];
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = mx53_dram_size[0];
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = mx53_dram_size[1];
+ gd->dram[1].start = PHYS_SDRAM_2;
+ gd->dram[1].size = mx53_dram_size[1];
return 0;
}
* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
*/
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = 0x05e00000;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = 0x05e00000;
- gd->bd->bi_dram[1].start = 0x05f00000;
- gd->bd->bi_dram[1].size = 0x00001000;
+ gd->dram[1].start = 0x05f00000;
+ gd->dram[1].size = 0x00001000;
- gd->bd->bi_dram[2].start = 0x05f02000;
- gd->bd->bi_dram[2].size = 0x00efd000;
+ gd->dram[2].start = 0x05f02000;
+ gd->dram[2].size = 0x00efd000;
- gd->bd->bi_dram[3].start = 0x06e00000;
- gd->bd->bi_dram[3].size = 0x0060f000;
+ gd->dram[3].start = 0x06e00000;
+ gd->dram[3].size = 0x0060f000;
- gd->bd->bi_dram[4].start = 0x07410000;
- gd->bd->bi_dram[4].size = 0x1aaf0000;
+ gd->dram[4].start = 0x07410000;
+ gd->dram[4].size = 0x1aaf0000;
- gd->bd->bi_dram[5].start = 0x22000000;
- gd->bd->bi_dram[5].size = 0x1c000000;
+ gd->dram[5].start = 0x22000000;
+ gd->dram[5].size = 0x1c000000;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
- gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
+ gd->dram[0].start = KERNEL_TEXT_OFFSET;
+ gd->dram[0].size = gd->ram_size - gd->dram[0].start;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < nbanks; i++) {
- base[i] = gd->bd->bi_dram[i].start;
- size[i] = gd->bd->bi_dram[i].size;
+ base[i] = gd->dram[i].start;
+ size[i] = gd->dram[i].size;
}
fdt_fixup_memory_banks(blob, base, size, nbanks);
dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start;
- dram_regions_info.region[i].size = gd->bd->bi_dram[i].size;
- dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size;
+ dram_regions_info.region[i].addr = gd->dram[i].start;
+ dram_regions_info.region[i].size = gd->dram[i].size;
+ dram_regions_info.total_dram_size += gd->dram[i].size;
}
bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry,
static const char *get_board_name(void)
{
- if (gd->bd->bi_dram[0].size == SZ_128M)
+ if (gd->dram[0].size == SZ_128M)
return STR_BTTC;
return STR_BTT3;
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = mx53_dram_size[0];
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = mx53_dram_size[0];
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = mx53_dram_size[1];
+ gd->dram[1].start = PHYS_SDRAM_2;
+ gd->dram[1].size = mx53_dram_size[1];
return 0;
}
{
phys_size_t ram_size = gd->ram_size;
- gd->bd->bi_dram[0].start = 0;
+ gd->dram[0].start = 0;
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
ram_size += CONFIG_SYS_MEM_TOP_HIDE;
case DRAM_1GB_SIZE:
case DRAM_2GB_ECC_SIZE:
case DRAM_2GB_SIZE:
- gd->bd->bi_dram[0].size = ram_size;
- gd->bd->bi_dram[1].start = 0;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[0].size = ram_size;
+ gd->dram[1].start = 0;
+ gd->dram[1].size = 0;
break;
case DRAM_4GB_ECC_SIZE:
- gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
- gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
- gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
+ gd->dram[0].size = DRAM_2GB_SIZE;
+ gd->dram[1].start = DRAM_4GB_SIZE;
+ gd->dram[1].size = DRAM_2GB_SIZE -
(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
break;
case DRAM_4GB_SIZE:
- gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
- gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
- gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
+ gd->dram[0].size = DRAM_2GB_SIZE;
+ gd->dram[1].start = DRAM_4GB_SIZE;
+ gd->dram[1].size = DRAM_2GB_SIZE;
break;
default:
- gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
- gd->bd->bi_dram[1].start = 0;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[0].size = DRAM_1GB_SIZE;
+ gd->dram[1].start = 0;
+ gd->dram[1].size = 0;
break;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
int board_init(void)
{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+ gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_size(gd->dram[0].size + gd->dram[1].size, "");
print_ddr_info(0);
}
ft_cpu_setup(blob, bd);
/* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
u8 reg;
/* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
u64 size[CONFIG_NR_DRAM_BANKS];
/* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
u64 size[CONFIG_NR_DRAM_BANKS];
/* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
u8 reg;
/* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
u64 size[CONFIG_NR_DRAM_BANKS];
/* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
void detail_board_ddr_info(void)
{
puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_size(gd->dram[0].size + gd->dram[1].size, "");
print_ddr_info(0);
}
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- base[i] = gd->bd->bi_dram[i].start;
- size[i] = gd->bd->bi_dram[i].size;
+ base[i] = gd->dram[i].start;
+ size[i] = gd->dram[i].size;
}
#ifdef CONFIG_RESV_RAM
void detail_board_ddr_info(void)
{
puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_size(gd->dram[0].size + gd->dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->dram[2].size) {
puts("\nDP-DDR ");
- print_size(gd->bd->bi_dram[2].size, "");
+ print_size(gd->dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
#endif
ft_cpu_setup(blob, bd);
/* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
void detail_board_ddr_info(void)
{
puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_size(gd->dram[0].size + gd->dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
+ if (soc_has_dp_ddr() && gd->dram[2].size) {
puts("\nDP-DDR ");
- print_size(gd->bd->bi_dram[2].size, "");
+ print_size(gd->dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
#endif
size = calloc(total_memory_banks, sizeof(u64));
/* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
+ base[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
+ base[1] = gd->dram[1].start;
+ size[1] = gd->dram[1].size;
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
puts("\nDDR ");
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- ddr_size += gd->bd->bi_dram[i].size;
+ ddr_size += gd->dram[i].size;
print_size(ddr_size, "");
print_ddr_info(0);
}
/* fixup DT for the three GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- base[i] = gd->bd->bi_dram[i].start;
- size[i] = gd->bd->bi_dram[i].size;
+ base[i] = gd->dram[i].start;
+ size[i] = gd->dram[i].size;
}
#ifdef CONFIG_RESV_RAM
{
u8 ram_size;
- memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS);
+ memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS);
if (!IS_ENABLED(CONFIG_CPU_V7R))
return fdtdec_setup_memory_banksize();
ram_size = phytec_get_am62_ddr_size_default();
switch (ram_size) {
case EEPROM_RAM_SIZE_1GB:
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x40000000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x40000000;
gd->ram_size = 0x40000000;
break;
case EEPROM_RAM_SIZE_2GB:
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x80000000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
break;
case EEPROM_RAM_SIZE_4GB:
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x80000000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR upper region */
- gd->bd->bi_dram[1].start = 0x880000000;
- gd->bd->bi_dram[1].size = 0x80000000;
+ gd->dram[1].start = 0x880000000;
+ gd->dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
break;
default:
/* Continue with default 2GB setup */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x80000000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
printf("DDR size %d is not supported\n", ram_size);
}
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start[bank] = gd->bd->bi_dram[bank].start;
- size[bank] = gd->bd->bi_dram[bank].size;
+ start[bank] = gd->dram[bank].start;
+ size[bank] = gd->dram[bank].size;
}
ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS);
{
u8 ram_size;
- memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS);
+ memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS);
if (!IS_ENABLED(CONFIG_CPU_V7R))
return fdtdec_setup_memory_banksize();
ram_size = phytec_get_am64_ddr_size_default();
switch (ram_size) {
case EEPROM_RAM_SIZE_1GB:
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x40000000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x40000000;
gd->ram_size = 0x40000000;
break;
case EEPROM_RAM_SIZE_2GB:
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x80000000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
break;
default:
/* Continue with default 2GB setup */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x80000000;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
printf("DDR size %d is not supported\n", ram_size);
}
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start[bank] = gd->bd->bi_dram[bank].start;
- size[bank] = gd->bd->bi_dram[bank].size;
+ start[bank] = gd->dram[bank].start;
+ size[bank] = gd->dram[bank].size;
}
return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS);
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
/* Update gd->ram_size to reflect total RAM across all banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- if (gd->bd->bi_dram[i].size == 0)
+ if (gd->dram[i].size == 0)
break;
- total_size += gd->bd->bi_dram[i].size;
+ total_size += gd->dram[i].size;
}
gd->ram_size = total_size;
return 0;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (gd->bd->bi_dram[bank].start != 0x48000000)
+ if (gd->dram[bank].start != 0x48000000)
continue;
/*
* If this U-Boot runs in EL3, make the bottom 128 MiB
* available for loading of follow up firmware blobs.
*/
- gd->bd->bi_dram[bank].start -= 0x8000000;
- gd->bd->bi_dram[bank].size += 0x8000000;
+ gd->dram[bank].start -= 0x8000000;
+ gd->dram[bank].size += 0x8000000;
break;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = gd->ram_base;
+ gd->dram[0].size = gd->ram_size;
return 0;
}
/* 16 GiB device, adjust memory map. */
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (gd->bd->bi_dram[bank].start == 0x480000000ULL)
- gd->bd->bi_dram[bank].size = 0x180000000ULL;
- else if (gd->bd->bi_dram[bank].start == 0x600000000ULL)
- gd->bd->bi_dram[bank].size = 0x200000000ULL;
+ if (gd->dram[bank].start == 0x480000000ULL)
+ gd->dram[bank].size = 0x180000000ULL;
+ else if (gd->dram[bank].start == 0x600000000ULL)
+ gd->dram[bank].size = 0x200000000ULL;
}
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ gd->dram[0].start = PHYS_SDRAM;
+ gd->dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ gd->dram[0].start = PHYS_SDRAM;
+ gd->dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
return 0;
}
addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- gd->bd->bi_dram[i].start = addr;
- gd->bd->bi_dram[i].size = size;
+ gd->dram[i].start = addr;
+ gd->dram[i].size = size;
}
return 0;
ulong size = CONFIG_SYS_MEM_TOP_HIDE;
gd->ram_size -= size;
- gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
+ gd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
#endif
exynos_init();
addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
- gd->bd->bi_dram[i].start = addr;
- gd->bd->bi_dram[i].size = size;
+ gd->dram[i].start = addr;
+ gd->dram[i].size = size;
}
return 0;
unsigned int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = mem_map[i + 1].phys;
- gd->bd->bi_dram[i].size = mem_map[i + 1].size;
+ gd->dram[i].start = mem_map[i + 1].phys;
+ gd->dram[i].size = mem_map[i + 1].size;
}
return 0;
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->dram[1].start = PHYS_SDRAM_2;
+ gd->dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->dram[2].start = PHYS_SDRAM_3;
+ gd->dram[2].size = PHYS_SDRAM_3_SIZE;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+ gd->dram[1].start = PHYS_SDRAM_2;
+ gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
+ gd->dram[2].start = PHYS_SDRAM_3;
+ gd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
PHYS_SDRAM_3_SIZE);
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
+ gd->dram[3].start = PHYS_SDRAM_4;
+ gd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
PHYS_SDRAM_4_SIZE);
return 0;
if (gd->ram_size > SZ_2G) {
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = SZ_2G;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = SZ_2G;
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
- gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+ gd->dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->dram[1].size = gd->ram_size - SZ_2G;
} else {
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = gd->ram_size;
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = 0;
- gd->bd->bi_dram[1].size = 0;
+ gd->dram[1].start = 0;
+ gd->dram[1].size = 0;
}
return 0;
struct draminfo_entry *ent = synquacer_draminfo->entry;
int i;
- for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+ for (i = 0; i < ARRAY_SIZE(gd->dram); i++) {
if (i < synquacer_draminfo->nr_regions) {
debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
- gd->bd->bi_dram[i].start = ent[i].base;
- gd->bd->bi_dram[i].size = ent[i].size;
+ gd->dram[i].start = ent[i].base;
+ gd->dram[i].size = ent[i].size;
}
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->dram[0].start = PHYS_SDRAM_1;
+ gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
if (t->hdr.tag != ATAG_MEM)
continue;
- gd->bd->bi_dram[bank].start = t->u.mem.start;
- gd->bd->bi_dram[bank].size = t->u.mem.size;
+ gd->dram[bank].start = t->u.mem.start;
+ gd->dram[bank].size = t->u.mem.size;
if (++bank == CONFIG_NR_DRAM_BANKS)
break;
}
ram_size = board_ti_get_emif_size();
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_effective_memsize();
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = get_effective_memsize();
if (ram_size > CFG_MAX_MEM_MAPPED) {
- gd->bd->bi_dram[1].start = 0x200000000;
- gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;
+ gd->dram[1].start = 0x200000000;
+ gd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;
}
return 0;
}
nbanks = 1;
- start[0] = bd->bi_dram[0].start;
- size[0] = bd->bi_dram[0].size;
+ start[0] = gd->dram[0].start;
+ size[0] = gd->dram[0].size;
/* adjust memory start address for LPAE */
if (lpae) {
* Reserve 1MB of memory for M4 (1MiB is also the minimum
* alignment for Linux due to MMU section size restrictions).
*/
- start[0] = gd->bd->bi_dram[0].start;
+ start[0] = gd->dram[0].start;
size[0] = SZ_256M - SZ_1M;
/* If needed, create a second entry for memory beyond 256M */
- if (gd->bd->bi_dram[0].size > SZ_256M) {
- start[1] = gd->bd->bi_dram[0].start + SZ_256M;
- size[1] = gd->bd->bi_dram[0].size - SZ_256M;
+ if (gd->dram[0].size > SZ_256M) {
+ start[1] = gd->dram[0].start + SZ_256M;
+ size[1] = gd->dram[0].size - SZ_256M;
areas = 2;
}
printf("Error setting up memory banksize. %d\n", ret);
/* Use the detected RAM size, we only support 1 bank right now. */
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].size = gd->ram_size;
return ret;
}
printf("Error setting up memory banksize. %d\n", ret);
/* Use the detected RAM size, we only support 1 bank right now. */
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].size = gd->ram_size;
return ret;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_size(gd->dram[0].size + gd->dram[1].size, "");
print_ddr_info(0);
}
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- base[i] = gd->bd->bi_dram[i].start;
- size[i] = gd->bd->bi_dram[i].size;
+ base[i] = gd->dram[i].start;
+ size[i] = gd->dram[i].size;
/* reduce size if reserved memory is within this bank */
if (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i))
size[i] = gd->arch.resv_ram - base[i];
* This validation is just for PS DDR.
* TODO: Update this for PL DDR check as well.
*/
- if (part_load_addr < gd->bd->bi_dram[0].start &&
+ if (part_load_addr < gd->dram[0].start &&
((part_load_addr + part_data_len) >
- (gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size))) {
+ (gd->dram[0].start +
+ gd->dram[0].size))) {
printf("INVALID_LOAD_ADDRESS_FAIL\n");
return -1;
}
#else
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_effective_memsize();
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].size = get_effective_memsize();
mem_map_fill();
#if defined(CFG_SYS_SDRAM_BASE)
return CFG_SYS_SDRAM_BASE;
#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
- return gd->bd->bi_dram[0].start;
+ return gd->dram[0].start;
#else
return 0;
#endif
of_start = NULL;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- start = gd->bd->bi_dram[bank].start;
- size = gd->bd->bi_dram[bank].size;
+ start = gd->dram[bank].start;
+ size = gd->dram[bank].size;
/* DRAM bank addresses are too low, skip it. */
if (start + size < low)
printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
}
-static void print_bi_dram(const struct bd_info *bd)
+static void print_dram(const struct bd_info *bd)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
- if (bd->bi_dram[i].size) {
+ if (gd->dram[i].size) {
bdinfo_print_num_l("DRAM bank", i);
- bdinfo_print_num_ll("-> start", bd->bi_dram[i].start);
- bdinfo_print_num_ll("-> size", bd->bi_dram[i].size);
+ bdinfo_print_num_ll("-> start", gd->dram[i].start);
+ bdinfo_print_num_ll("-> size", gd->dram[i].size);
}
}
}
bdinfo_print_num_l("bd address", (ulong)bd);
#endif
bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params);
- print_bi_dram(bd);
+ print_dram(bd);
bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart);
bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize);
bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset);
print_eth();
return CMD_RET_SUCCESS;
case 'm':
- print_bi_dram(bd);
+ print_dram(bd);
return CMD_RET_SUCCESS;
default:
return CMD_RET_USAGE;
return CMD_RET_FAILURE;
}
- if (!((start_addr >= gd->bd->bi_dram[0].start &&
- (start_addr <= (gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - 1))) ||
- (start_addr >= gd->bd->bi_dram[1].start &&
- (start_addr <= (gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size - 1))))) {
+ if (!((start_addr >= gd->dram[0].start &&
+ (start_addr <= (gd->dram[0].start + gd->dram[0].size - 1))) ||
+ (start_addr >= gd->dram[1].start &&
+ (start_addr <= (gd->dram[1].start + gd->dram[1].size - 1))))) {
puts("Address is not in the DDR range\n");
return CMD_RET_FAILURE;
}
printf("CPU: " RESET CONFIG_SYS_ARCH " (%d cores, 1 in use)\n", n_cpus);
break;
case MEMORY:
- for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++)
- size += gd->bd->bi_dram[j].size;
+ for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->dram[j].size; j++)
+ size += gd->dram[j].size;
printf("Memory:" RESET " ");
print_size(size, "\n");
break;
debug("\nRAM Configuration:\n");
for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- size += gd->bd->bi_dram[i].size;
+ size += gd->dram[i].size;
debug("Bank #%d: %llx ", i,
- (unsigned long long)(gd->bd->bi_dram[i].start));
+ (unsigned long long)(gd->dram[i].start));
#ifdef DEBUG
- print_size(gd->bd->bi_dram[i].size, "\n");
+ print_size(gd->dram[i].size, "\n");
#endif
}
debug("\nDRAM: ");
__weak int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = get_effective_memsize();
+ gd->dram[0].start = gd->ram_base;
+ gd->dram[0].size = get_effective_memsize();
return 0;
}
void handoff_save_dram(struct spl_handoff *ho)
{
- struct bd_info *bd = gd->bd;
int i;
ho->ram_size = gd->ram_size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- ho->ram_bank[i].start = bd->bi_dram[i].start;
- ho->ram_bank[i].size = bd->bi_dram[i].size;
+ ho->ram_bank[i].start = gd->dram[i].start;
+ ho->ram_bank[i].size = gd->dram[i].size;
}
}
void handoff_load_dram_banks(struct spl_handoff *ho)
{
- struct bd_info *bd = gd->bd;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- bd->bi_dram[i].start = ho->ram_bank[i].start;
- bd->bi_dram[i].size = ho->ram_bank[i].size;
+ gd->dram[i].start = ho->ram_bank[i].start;
+ gd->dram[i].size = ho->ram_bank[i].size;
}
}
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- size += gd->bd->bi_dram[i].size;
+ size += gd->dram[i].size;
save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
writel(a, save_addr);
writel(CONFIG_SYS_BOOTCOUNT_MAGIC, &save_addr[1]);
int i, tmp;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- size += gd->bd->bi_dram[i].size;
+ size += gd->dram[i].size;
save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
counter = readl(&save_addr[0]);
/* Get bank configuration from devicetree */
ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
- (phys_size_t *)&gd->ram_size, &bd);
+ (phys_size_t *)&gd->ram_size, gd);
if (ret) {
puts("DDR: Failed to decode memory node\n");
return -ENXIO;
sdram_set_firewall(&bd);
- priv->info.base = bd.bi_dram[0].start;
+ priv->info.base = gd->dram[0].start;
priv->info.size = gd->ram_size;
debug("DDR: HMC init success\n");
/* Get bank configuration from devicetree */
ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
- (phys_size_t *)&gd->ram_size, gd->bd);
+ (phys_size_t *)&gd->ram_size, gd);
if (ret) {
puts("DDR: Failed to decode memory node\n");
ret = -ENXIO;
for (i = 0; i < config_dram_banks; i++) {
remaining_size = hw_size - size_counter;
if (remaining_size <= dram_bank_info[i].max_size) {
- gd->bd->bi_dram[i].start = dram_bank_info[i].start;
- gd->bd->bi_dram[i].size = remaining_size;
+ gd->dram[i].start = dram_bank_info[i].start;
+ gd->dram[i].size = remaining_size;
debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n",
- i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+ i, gd->dram[i].start, gd->dram[i].size);
break;
}
- gd->bd->bi_dram[i].start = dram_bank_info[i].start;
- gd->bd->bi_dram[i].size = dram_bank_info[i].max_size;
+ gd->dram[i].start = dram_bank_info[i].start;
+ gd->dram[i].size = dram_bank_info[i].max_size;
debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n",
- i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
- size_counter += gd->bd->bi_dram[i].size;
+ i, gd->dram[i].start, gd->dram[i].size);
+ size_counter += gd->dram[i].size;
}
gd->ram_size = hw_size;
printf("DDR: firewall init success\n");
- priv->info.base = gd->bd->bi_dram[0].start;
+ priv->info.base = gd->dram[0].start;
priv->info.size = gd->ram_size;
/* Ending DDR driver initialization success tracking */
/* Get bank configuration from devicetree */
ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
- (phys_size_t *)&gd->ram_size, &bd);
+ (phys_size_t *)&gd->ram_size, gd);
if (ret) {
printf("%s: Failed to decode memory node\n", memory_type_in_use(dev));
printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM"));
- priv->info.base = bd.bi_dram[0].start;
+ priv->info.base = gd->dram[0].start;
priv->info.size = gd->ram_size;
/* Ending DDR driver initialization success tracking */
debug("DDR: Running SDRAM size sanity check\n");
- ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start,
- gd->bd->bi_dram[0].size);
- if (ram_check != gd->bd->bi_dram[0].size) {
+ ram_check = get_ram_size((long *)gd->dram[0].start,
+ gd->dram[0].size);
+ if (ram_check != gd->dram[0].size) {
puts("DDR: SDRAM size check failed!\n");
hang();
}
/* setup the dram info within bd */
dram_init_banksize();
- if (gd->ram_size != gd->bd->bi_dram[0].size) {
+ if (gd->ram_size != gd->dram[0].size) {
printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n",
- gd->bd->bi_dram[0].size >> 20);
+ gd->dram[0].size >> 20);
printf(" mismatch with hardware (%ld MiB).\n",
gd->ram_size >> 20);
}
- if (gd->bd->bi_dram[0].size > gd->ram_size) {
+ if (gd->dram[0].size > gd->ram_size) {
printf("DDR: Error: DRAM size from device tree is greater\n");
printf(" than hardware size.\n");
hang();
/* Get bank configuration from devicetree */
ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
- (phys_size_t *)&gd->ram_size, &bd);
+ (phys_size_t *)&gd->ram_size, gd);
if (ret) {
debug("%s: Failed to decode memory node\n", __func__);
return -1;
printf("DDR: %lld MiB\n", gd->ram_size >> 20);
- priv->info.base = bd.bi_dram[0].start;
+ priv->info.base = gd->dram[0].start;
priv->info.size = gd->ram_size;
sdram_size_check(&bd);
/* Get bank configuration from devicetree */
ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
- (phys_size_t *)&gd->ram_size, &bd);
+ (phys_size_t *)&gd->ram_size, gd);
if (ret) {
puts("DDR: Failed to decode memory node\n");
return -1;
sdram_size_check(&bd);
- priv->info.base = bd.bi_dram[0].start;
+ priv->info.base = gd->dram[0].start;
priv->info.size = gd->ram_size;
debug("DDR: HMC init success\n");
icache_enable();
- start_addr = bd->bi_dram[0].start;
- size = bd->bi_dram[0].size;
+ start_addr = gd->dram[0].start;
+ size = gd->dram[0].size;
/* Initialize small block for page table */
memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
if (bank >= CONFIG_NR_DRAM_BANKS)
break;
- start_addr = bd->bi_dram[bank].start;
- size = bd->bi_dram[bank].size;
+ start_addr = gd->dram[bank].start;
+ size = gd->dram[bank].size;
}
dcache_disable();
phys_addr_t start = 0;
phys_size_t remaining_size;
- start = bd->bi_dram[bank].start;
- remaining_size = bd->bi_dram[bank].size;
+ start = gd->dram[bank].start;
+ remaining_size = gd->dram[bank].size;
debug("Checking bank %d: start=0x%llx, size=0x%llx\n",
bank, start, remaining_size);
- while (ram_check < bd->bi_dram[bank].size) {
+ while (ram_check < gd->dram[bank].size) {
phys_size_t size, test_size, detected_size;
size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size);
}
ram_check += detected_size;
- remaining_size = bd->bi_dram[bank].size - ram_check;
+ remaining_size = gd->dram[bank].size - ram_check;
}
total_ram_check += ram_check;
u32 lower, upper;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- if (!bd->bi_dram[i].size)
+ if (!gd->dram[i].size)
continue;
- value = bd->bi_dram[i].start;
+ value = gd->dram[i].start;
/* Keep first 1MB of SDRAM memory region as secure region when
* using ATF flow, where the ATF code is located.
(i * 4 * sizeof(u32)));
/* Setting non-secure MPU limit and limit extended */
- value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
+ value = gd->dram[i].start + gd->dram[i].size - 1;
lower = lower_32_bits(value);
upper = upper_32_bits(value);
phys_size_t value;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- if (!bd->bi_dram[i].size)
+ if (!gd->dram[i].size)
continue;
- value = bd->bi_dram[i].start;
+ value = gd->dram[i].start;
/* Keep first 1MB of SDRAM memory region as secure region when
* using ATF flow, where the ATF code is located.
(i * 4 * sizeof(u32)));
/* Setting limit and limit extended */
- value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
+ value = gd->dram[i].start + gd->dram[i].size - 1;
lower = lower_32_bits(value);
upper = upper_32_bits(value);
break;
}
- size = gd->bd->bi_dram[i].size;
- base = gd->bd->bi_dram[i].start;
+ size = gd->dram[i].size;
+ base = gd->dram[i].start;
if (size && attrib) {
mvebu_mmc_write(mmc, WINDOW_CTRL(i),
MVCPU_WIN_CTRL_DATA(size,
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
/* Get bank base and size */
- win_param.base_addr = gd->bd->bi_dram[i].start;
- win_param.size = gd->bd->bi_dram[i].size;
+ win_param.base_addr = gd->dram[i].start;
+ win_param.size = gd->dram[i].size;
if (win_param.size == 0)
win_param.enable = 0;
else
return 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
- if (bd->bi_dram[i].size) {
- phys_addr_t start = bd->bi_dram[i].start;
+ if (gd->dram[i].size) {
+ phys_addr_t start = gd->dram[i].start;
if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
- start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
+ start = virt_to_phys((void *)(uintptr_t)gd->dram[i].start);
pci_set_region(hose->regions + hose->region_count++,
- start, start, bd->bi_dram[i].size,
+ start, start, gd->dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
}
}
break;
}
- size = gd->bd->bi_dram[i].size;
- base = gd->bd->bi_dram[i].start;
+ size = gd->dram[i].size;
+ base = gd->dram[i].start;
if ((size) && (attrib))
writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, MVCPU_WIN_ENABLE),
meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize *
((1 << VPU_MAX_LOG2_BPP) / 8) +
MESON_VPU_OVERSCAN, EFI_PAGE_SIZE);
- meson_fb.base = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size - meson_fb.fb_size;
+ meson_fb.base = gd->dram[0].start +
+ gd->dram[0].size - meson_fb.fb_size;
/* Override the framebuffer address */
uc_plat->base = meson_fb.base;
* at the end of the RAM and we strip this portion from the kernel
* allowed region
*/
- mem_start = gd->bd->bi_dram[0].start;
- mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size;
+ mem_start = gd->dram[0].start;
+ mem_size = gd->dram[0].size - meson_fb.fb_size;
ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1);
if (ret) {
eprintf("Cannot setup simplefb: Error reserving memory\n");
return 0; /* Keep older kernels working */
}
- start = gd->bd->bi_dram[0].start;
+ start = gd->dram[0].start;
size = de2_plat->base - start;
ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
if (ret) {
* and e.g. Linux refuses to iomap RAM on ARM, see:
* linux/arch/arm/mm/ioremap.c around line 301.
*/
- start = gd->bd->bi_dram[0].start;
+ start = gd->dram[0].start;
size = sunxi_display->fb_addr - start;
ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
if (ret) {
*/
struct upl *upl;
#endif
+ /**
+ * @dram: array describing DRAM banks (start address and size for each bank)
+ */
+ struct { /* RAM configuration */
+ phys_addr_t start;
+ phys_size_t size;
+ } dram[CONFIG_NR_DRAM_BANKS];
};
#ifndef DO_DEPS_ONLY
static_assert(sizeof(struct global_data) == GD_SIZE);
#endif
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
- struct { /* RAM configuration */
- phys_addr_t start;
- phys_size_t size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
};
#endif /* __ASSEMBLY__ */
* Memory configurations
*/
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_1_SIZE (gd->dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_2_SIZE (gd->dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_1_SIZE (gd->dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_2_SIZE (gd->dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_1_SIZE (gd->dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_2_SIZE (gd->dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_1_SIZE (gd->dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_2_SIZE (gd->dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
};
struct bd_info;
+struct global_data;
/**
* enum fdt_source_t - indicates where the devicetree came from
int fdtdec_setup_mem_size_base_lowest(void);
/**
- * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
+ * fdtdec_setup_memory_banksize() - decode and populate gd->dram
*
* Decode the /memory 'reg' property to determine the address and size of the
* memory banks. Use this data to populate the global data board info with the
* @param basep Returns base address of first memory bank (NULL to
* ignore)
* @param sizep Returns total memory size (NULL to ignore)
- * @param bd Updated with the memory bank information (NULL to skip)
+ * @param gd_ptr Updated with the memory bank information (NULL to skip)
* Return: 0 if OK, -ve on error
*/
int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
phys_addr_t *basep, phys_size_t *sizep,
- struct bd_info *bd);
+ struct global_data *gd_ptr);
/**
* fdtdec_get_srcname() - Get the name of where the devicetree comes from
* dram_init_banksize() - Set up DRAM bank sizes
*
* This can be implemented by boards to set up the DRAM bank information in
- * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
+ * gd->dram[] It is called just before relocation, after dram_init()
* is called.
*
* If this is not provided, a default implementation will try to set up a
#include <linux/ctype.h>
#include <linux/lzo.h>
#include <linux/ioport.h>
+#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
if (ret != 0)
return -EINVAL;
- gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
- gd->bd->bi_dram[bank].size =
+ gd->dram[bank].start = (phys_addr_t)res.start;
+ gd->dram[bank].size =
(phys_size_t)(res.end - res.start + 1);
debug("%s: DRAM Bank #%d: start = %pap, size = %pap\n",
__func__, bank,
- &gd->bd->bi_dram[bank].start,
- &gd->bd->bi_dram[bank].size);
+ &gd->dram[bank].start,
+ &gd->dram[bank].size);
}
return 0;
int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
phys_addr_t *basep, phys_size_t *sizep,
- struct bd_info *bd)
+ gd_t *gd_ptr)
{
int addr_cells, size_cells;
const u32 *cell, *end;
}
/* Note: if no matching subnode was found we use the parent node */
- if (bd) {
- memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) *
+ if (gd_ptr) {
+ memset(gd_ptr->dram, '\0', sizeof(gd_ptr->dram[0]) *
CONFIG_NR_DRAM_BANKS);
}
if (addr_cells == 2)
addr += (u64)fdt32_to_cpu(*cell++) << 32UL;
addr += fdt32_to_cpu(*cell++);
- if (bd)
- bd->bi_dram[bank].start = addr;
+ if (gd_ptr)
+ gd_ptr->dram[bank].start = addr;
if (basep && !bank)
*basep = (phys_addr_t)addr;
}
}
- if (bd)
- bd->bi_dram[bank].size = size;
+ if (gd_ptr)
+ gd_ptr->dram[bank].size = size;
total_size += size;
}
#endif
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (!gd->bd->bi_dram[bank].size ||
- rsv_start < gd->bd->bi_dram[bank].start)
+ if (!gd->dram[bank].size ||
+ rsv_start < gd->dram[bank].start)
continue;
/* Watch out for RAM at end of address space! */
- bank_end = gd->bd->bi_dram[bank].start +
- gd->bd->bi_dram[bank].size - 1;
+ bank_end = gd->dram[bank].start +
+ gd->dram[bank].size - 1;
if (rsv_start > bank_end)
continue;
if (bank_end > end)
phys_addr_t bank_end;
phys_size_t size;
u64 ram_top = gd->ram_top;
- struct bd_info *bd = gd->bd;
if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP))
return lmb_arch_add_memory();
ram_top = 0x100000000ULL;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- size = bd->bi_dram[i].size;
+ size = gd->dram[i].size;
if (size) {
- lmb_add(bd->bi_dram[i].start, size);
+ lmb_add(gd->dram[i].start, size);
if (!IS_ENABLED(CONFIG_LMB_LIMIT_DMA_BELOW_RAM_TOP))
continue;
- bank_end = bd->bi_dram[i].start + size;
+ bank_end = gd->dram[i].start + size;
/*
* Reserve memory above ram_top as
* no-overwrite so that it cannot be
* allocated
*/
- if (bd->bi_dram[i].start >= ram_top)
- lmb_reserve(bd->bi_dram[i].start, size,
+ if (gd->dram[i].start >= ram_top)
+ lmb_reserve(gd->dram[i].start, size,
LMB_NOOVERWRITE);
else if (bank_end > ram_top)
lmb_reserve(ram_top, bank_end - ram_top,
static int bdinfo_check_mem(struct unit_test_state *uts)
{
- struct bd_info *bd = gd->bd;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
- if (bd->bi_dram[i].size) {
+ if (gd->dram[i].size) {
ut_assertok(test_num_l(uts, "DRAM bank", i));
ut_assertok(test_num_ll(uts, "-> start",
- bd->bi_dram[i].start));
+ gd->dram[i].start));
ut_assertok(test_num_ll(uts, "-> size",
- bd->bi_dram[i].size));
+ gd->dram[i].size));
}
}
projects / thirdparty / u-boot.git / commitdiff
