drm/msm/dsi: add support for DSI-PHY on Milos

Add DSI PHY support for the Milos platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Patchwork: https://patchwork.freedesktop.org/patch/722319/
Link: https://lore.kernel.org/r/20260501-milos-mdss-v3-6-58bfc58c0e13@fairphone.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index c59375aaae19740275c05a532ecb465af463cfe3..1fb3899b88bf2638ff4075fffa867a3d33a0fac1 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -571,6 +571,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
          .data = &dsi_phy_5nm_8350_cfgs },
        { .compatible = "qcom,sm8450-dsi-phy-5nm",
          .data = &dsi_phy_5nm_8450_cfgs },
+       { .compatible = "qcom,milos-dsi-phy-4nm",
+         .data = &dsi_phy_4nm_milos_cfgs },
        { .compatible = "qcom,sm8550-dsi-phy-4nm",
          .data = &dsi_phy_4nm_8550_cfgs },
        { .compatible = "qcom,sm8650-dsi-phy-4nm",

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index c01784ca38edc7ba119cf59d293c4bce902fa394..21a59d66e8dc5568cbb66eca4fea787228360d74 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -61,6 +61,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 8f4b03713f25678667fcf7daec494177e6f42431..984a66085dfbf86c99292a9a26685bc7db02a5c8 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -1436,6 +1436,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = {
        .quirks = DSI_PHY_7NM_QUIRK_V5_2,
 };
 
+const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs = {
+       .has_phy_lane = true,
+       .regulator_data = dsi_phy_7nm_98000uA_regulators,
+       .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
+       .ops = {
+               .enable = dsi_7nm_phy_enable,
+               .disable = dsi_7nm_phy_disable,
+               .pll_init = dsi_pll_7nm_init,
+               .save_pll_state = dsi_7nm_pll_save_state,
+               .restore_pll_state = dsi_7nm_pll_restore_state,
+               .set_continuous_clock = dsi_7nm_set_continuous_clock,
+       },
+       .min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+       .max_pll_rate = 5000000000UL,
+#else
+       .max_pll_rate = ULONG_MAX,
+#endif
+       .io_start = { 0xae95000 },
+       .num_dsi_phy = 1,
+       .quirks = DSI_PHY_7NM_QUIRK_V5_2,
+};
+
 const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
        .has_phy_lane = true,
        .regulator_data = dsi_phy_7nm_98400uA_regulators,