memop, result, fi);
}
-static hwaddr arm_cpu_get_phys_page(CPUARMState *env, vaddr addr,
+static hwaddr arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr,
MemTxAttrs *attrs, ARMMMUIdx mmu_idx)
{
S1Translate ptw = {
CPUARMState *env = &cpu->env;
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
- hwaddr res = arm_cpu_get_phys_page(env, addr, attrs, mmu_idx);
+ hwaddr res = arm_cpu_get_phys_addr(env, addr, attrs, mmu_idx);
if (res != -1) {
return res;
switch (mmu_idx) {
case ARMMMUIdx_E10_1:
case ARMMMUIdx_E10_1_PAN:
- return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E10_0);
+ return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E10_0);
case ARMMMUIdx_E20_2:
case ARMMMUIdx_E20_2_PAN:
- return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E20_0);
+ return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E20_0);
default:
return -1;
}