drm/amdgpu/hdp6.0: do a posting read when flushing HDP

[ Upstream commit abe1cbaec6cfe9fde609a15cd6a12c812282ce77 ]

Need to read back to make sure the write goes through.

Cc: David Belanger <david.belanger@amd.com>
Reviewed-by: Frank Min <frank.min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
index 53ad93f96cd9189debb980df9fc05c8d762d16aa..b6d71ec1debf9afc7ce8efac0bd2646156ff8ac9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
@@ -31,10 +31,12 @@
 static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
                                struct amdgpu_ring *ring)
 {
-       if (!ring || !ring->funcs->emit_wreg)
+       if (!ring || !ring->funcs->emit_wreg) {
                WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-       else
+               RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+       } else {
                amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+       }
 }
 
 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,